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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2016-12-21 11:26:56 +0100
committerStephen Boyd <sboyd@codeaurora.org>2017-02-14 10:59:15 -0800
commit1006ccccd03c0e420bf0398a5ab944759268f387 (patch)
treeafade80ca4e2bb86afbd7c5b328043cac4b9979e /drivers/clk/mvebu
parent33707260422475385c6f33f526c71805a3dc5dab (diff)
clk: mvebu: adjust clock handling for the CP110 system controller
This commit: - makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP. - makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6) Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mvebu')
-rw-r--r--drivers/clk/mvebu/cp110-system-controller.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c
index 32e5b43c086f..6b11d7b3e0e0 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -64,8 +64,11 @@ enum {
#define CP110_GATE_NAND 2
#define CP110_GATE_PPV2 3
#define CP110_GATE_SDIO 4
+#define CP110_GATE_MG 5
+#define CP110_GATE_MG_CORE 6
#define CP110_GATE_XOR1 7
#define CP110_GATE_XOR0 8
+#define CP110_GATE_GOP_DP 9
#define CP110_GATE_PCIE_X1_0 11
#define CP110_GATE_PCIE_X1_1 12
#define CP110_GATE_PCIE_X4 13
@@ -73,7 +76,7 @@ enum {
#define CP110_GATE_SATA 15
#define CP110_GATE_SATA_USB 16
#define CP110_GATE_MAIN 17
-#define CP110_GATE_SDMMC 18
+#define CP110_GATE_SDMMC_GOP 18
#define CP110_GATE_SLOW_IO 21
#define CP110_GATE_USB3H0 22
#define CP110_GATE_USB3H1 23
@@ -296,6 +299,11 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
"gate-clock-output-names",
CP110_GATE_MAIN, &parent);
break;
+ case CP110_GATE_MG:
+ of_property_read_string_index(np,
+ "gate-clock-output-names",
+ CP110_GATE_MG_CORE, &parent);
+ break;
case CP110_GATE_NAND:
parent = nand_name;
break;
@@ -303,9 +311,10 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
parent = ppv2_name;
break;
case CP110_GATE_SDIO:
+ case CP110_GATE_GOP_DP:
of_property_read_string_index(np,
"gate-clock-output-names",
- CP110_GATE_SDMMC, &parent);
+ CP110_GATE_SDMMC_GOP, &parent);
break;
case CP110_GATE_XOR1:
case CP110_GATE_XOR0: