Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The usual collection of clk driver updates and new driver additions.
  In terms of lines it's mainly Qualcomm and Mediatek code, supporting
  various SoCs and their multitude of clk controllers.

  New Drivers:
   - GCC and RPMcc support for Qualcomm QCM2290 SoCs
   - GCC support for Qualcomm MSM8994/MSM8992 SoCs
   - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
   - Support for Mediatek MT8195 SoCs
   - Initial clock driver for the Exynos850 SoC
   - Add i.MX8ULP clock driver and related bindings

  Updates:
   - Clock power management for new SAMA7G5 SoC
   - Updates to the master clock driver and sam9x60-pll to be able to
     use cpufreq-dt driver and avoid overclocking of CPU and MCK0
     domains while changing the frequency via DVFS
   - Use ARRAY_SIZE in qcom clk drivers
   - Remove some impractical fallback parent names in qcom clk drivers
   - Make Mediatek clk drivers tristate
   - Refactoring of the CPU clock code and conversion of Samsung
     Exynos5433 CPU clock driver to the platform driver
   - A few conversions to devm_platform_ioremap_resource()
   - Updates of the Samsung Kconfig help text
   - Update video path realted clocks for Amlogic meson8
   - Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
   - Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
   - Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
   - Remove unused helpers from i.MX specific clock header
   - Rework all i.MX clk based helpers to use clk_hw based ones
   - Rework i.MX gate/mux/divider wrappers
   - Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
   - Update i.MX pllv4 and composite clocks to support i.MX8ULP
   - Disable i.MX7ULP composite clock during initialization
   - Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
   - Disable the i.MX pfd when set pfdv2 clock rate
   - Add support for i.MX8ULP in pfdv2
   - Add the pcc reset controller support on i.MX8ULP
   - Fix the build break when clk-imx8ulp is built as module
   - Move csi_sel mux to correct base register in i.MX6UL clock drivr
   - Fix csi clk gate register in i.MX6UL clock driver
   - Fix build bug making CLK_IMX8ULP select MXC_CLK
   - Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
   - Add Ethernet clocks on Renesas RZ/G2L
   - Move Rockchip to use module_platform_probe
   - Enable usage of Coresight related clocks on Rockchip rk3399"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits)
  clk: use clk_core_get_rate_recalc() in clk_rate_get()
  clk: at91: sama7g5: set low limit for mck0 at 32KHz
  clk: at91: sama7g5: remove prescaler part of master clock
  clk: at91: clk-master: add notifier for divider
  clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
  clk: at91: clk-master: fix prescaler logic
  clk: at91: clk-master: mask mckr against layout->mask
  clk: at91: clk-master: check if div or pres is zero
  clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
  clk: at91: pmc: add sama7g5 to the list of available pmcs
  clk: at91: clk-master: improve readability by using local variables
  clk: at91: clk-master: add register definition for sama7g5's master clock
  clk: at91: sama7g5: add securam's peripheral clock
  clk: at91: pmc: execute suspend/resume only for backup mode
  clk: at91: re-factor clocks suspend/resume
  clk: ux500: Add driver for the reset portions of PRCC
  dt-bindings: clock: u8500: Rewrite in YAML and extend
  clk: composite: Use rate_ops.determine_rate when also a mux is available
  clk: samsung: describe drivers in Kconfig
  clk: samsung: exynos5433: update apollo and atlas clock probing
  ...

1 files changed, 34 insertions, 9 deletions

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9ef007b3cf9b..74efc82127e1 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -324,6 +324,14 @@ config MSM_MMCC_8998
 	  Say Y if you want to support multimedia devices such as display,
 	  graphics, video encode/decode, camera, etc.
 
+config QCM_GCC_2290
+	tristate "QCM2290 Global Clock Controller"
+	select QCOM_GDSC
+	help
+	  Support for the global clock controller on QCM2290 devices.
+	  Say Y if you want to use multimedia devices or peripheral
+	  devices such as UART, SPI, I2C, USB, SD/eMMC etc.
+
 config QCS_GCC_404
 	tristate "QCS404 Global Clock Controller"
 	help
@@ -340,6 +348,15 @@ config SC_CAMCC_7180
 	  Say Y if you want to support camera devices and functionality such as
 	  capturing pictures.
 
+config SC_CAMCC_7280
+	tristate "SC7280 Camera Clock Controller"
+	select SC_GCC_7280
+	help
+	  Support for the camera clock controller on Qualcomm Technologies, Inc
+	  SC7280 devices.
+	  Say Y if you want to support camera devices and functionality such as
+	  capturing pictures.
+
 config SC_DISPCC_7180
 	tristate "SC7180 Display Clock Controller"
 	select SC_GCC_7180
@@ -385,15 +402,6 @@ config SC_GCC_8180X
 	  Say Y if you want to use peripheral devices such as UART, SPI,
 	  I2C, USB, UFS, SDCC, etc.
 
-config SC_LPASS_CORECC_7180
-	tristate "SC7180 LPASS Core Clock Controller"
-	select SC_GCC_7180
-	help
-	  Support for the LPASS(Low Power Audio Subsystem) core clock controller
-	  on SC7180 devices.
-	  Say Y if you want to use LPASS clocks and power domains of the LPASS
-	  core clock controller.
-
 config SC_GPUCC_7180
 	tristate "SC7180 Graphics Clock Controller"
 	select SC_GCC_7180
@@ -410,6 +418,23 @@ config SC_GPUCC_7280
 	  Say Y if you want to support graphics controller devices and
 	  functionality such as 3D graphics.
 
+config SC_LPASSCC_7280
+	tristate "SC7280 Low Power Audio Subsystem (LPASS) Clock Controller"
+	select SC_GCC_7280
+	help
+	  Support for the LPASS clock controller on SC7280 devices.
+	  Say Y if you want to use the LPASS branch clocks of the LPASS clock
+	  controller to reset the LPASS subsystem.
+
+config SC_LPASS_CORECC_7180
+	tristate "SC7180 LPASS Core Clock Controller"
+	select SC_GCC_7180
+	help
+	  Support for the LPASS(Low Power Audio Subsystem) core clock controller
+	  on SC7180 devices.
+	  Say Y if you want to use LPASS clocks and power domains of the LPASS
+	  core clock controller.
+
 config SC_MSS_7180
 	tristate "SC7180 Modem Clock Controller"
 	select SC_GCC_7180