summaryrefslogtreecommitdiff
path: root/drivers/clk/qcom/dispcc-qcm2290.c
diff options
context:
space:
mode:
authorGabor Juhos <j4g8y7@gmail.com>2024-10-28 19:48:18 +0100
committerBjorn Andersson <andersson@kernel.org>2024-12-26 16:43:04 -0600
commitb9286a91b59fe9c7f8e231fce8e51df3b1442f6b (patch)
tree5e64dc642d1ce629674d8cd068afa00c22e2fdae /drivers/clk/qcom/dispcc-qcm2290.c
parent5d11fd2a919b153c68cda42c175b4e45668654a9 (diff)
clk: qcom: dispcc-qcm2290: remove alpha values from disp_cc_pll0_config
Since both the 'alpha' and 'alpha_hi' members of the configuration is initialized (the latter is implicitly) with zero values, the output rate of the PLL will be the same whether alpha mode is enabled or not. Remove the initialization of the alpha* members to make it clear that the alpha mode is not required to get the desired output rate. Despite that enabling alpha mode is not needed for the initial configuration, the set_rate() op might require that it is enabled already. In this particular case however, the clk_alpha_pll_set_rate() function will get reset the ALPHA_EN bit when the PLL's rate changes, so dropping 'alpha_en_mask' is safe. No functional changes intended, compile tested only. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241028-alpha-mode-cleanup-v2-4-9bc6d712bd76@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/dispcc-qcm2290.c')
-rw-r--r--drivers/clk/qcom/dispcc-qcm2290.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index 449ffea2295d..d7bb1399e102 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -40,8 +40,6 @@ static const struct pll_vco spark_vco[] = {
/* 768MHz configuration */
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x28,
- .alpha = 0x0,
- .alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),