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authorClaudiu Beznea <claudiu.beznea@microchip.com>2021-10-11 14:27:08 +0300
committerStephen Boyd <sboyd@kernel.org>2021-10-26 18:27:42 -0700
commitc55388167775960412fe576a343f4c9001523786 (patch)
treedf66f03ab63225f2f87928449c0e5075e926ed78 /drivers/clk/renesas/r8a7743-cpg-mssr.c
parentc884c7a0acb29357d694ebafec8aa272015e7c52 (diff)
clk: at91: clk-master: add register definition for sama7g5's master clock
SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the register at offset 0x30 (relative to PMC). In the last/first phase of suspend/resume procedure (which is architecture specific) the parent of master clocks are changed (via assembly code) for more power saving (see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable and at91_mckx_ps_restore). Thus the macros corresponding to register at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S. commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's master clock") introduced the proper macros but didn't adapted the clk-master.c as well. Thus, this commit adapt the clk-master.c to use the macros introduced in commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's master clock"). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/renesas/r8a7743-cpg-mssr.c')
0 files changed, 0 insertions, 0 deletions