diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-11 14:59:44 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 12:27:45 +0200 |
| commit | 880c3fa319b24c1a8ccb4dfc171a3329ad14943a (patch) | |
| tree | 1296f8d4296caa0d87da1141e77ddfe24bab2fe8 /drivers/clk/renesas/r8a77990-cpg-mssr.c | |
| parent | 29db30c45f07c929c86c40a5b85f18b69c89c638 (diff) | |
clk: renesas: Move RPC core clocks
The RPC and RPCD2 core clocks were added to the sections for internal
core clocks, while they are core clock outputs, visible from DT.
Move them to the correct sections.
Rename the ".rpc" clock on R-Car S4 to "rpc".
Fixup nearby whitespace to increase uniformity.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas/r8a77990-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a77990-cpg-mssr.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index a5c95e0021f8..b666d099365e 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -110,10 +110,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078), DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c), - DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A77990_CLK_RPC), + DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77990_CLK_RPC), DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1), |