diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-02-14 11:02:07 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-03-06 10:42:14 +0100 |
| commit | 1f04b7939704fce82d2bb5ef5561e2499a91170a (patch) | |
| tree | 6d7f7bab257ff018d38609d1ff010c321c523ec7 /drivers/clk/renesas/r8a77995-cpg-mssr.c | |
| parent | 3c876432e772201dabe3d9d5585226be5f2b9a8c (diff) | |
clk: renesas: r8a77995: Fix VIN parent clock
According to the R-Car Series, 3rd Generation Hardware User’s Manual
Rev. 2.30, the parent clock of the Video Input Module (VIN) on R-Car D3
is S3D1. Update the driver to match the documentation.
This has no functional impact, as both S1D2 and S3D1 have the same clock
rate, and are always-on clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/9b655843a260e06fa6f3349cdafac180e2bf38a5.1676368776.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas/r8a77995-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 24ba9093a72f..3a73f6f911dd 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { DEF_MOD("du0", 724, R8A77995_CLK_S1D1), DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), DEF_MOD("mlp", 802, R8A77995_CLK_S2D1), - DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), + DEF_MOD("vin4", 807, R8A77995_CLK_S3D1), DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4), |