diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2021-03-15 16:56:07 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2021-03-21 11:10:58 +0100 |
| commit | a3561e77cf3ca0937227ba13744d84fc46e5eb4b (patch) | |
| tree | 14bb72f7a1a97dcf5fc532dff1d4beec99bb9bbb /drivers/clk/rockchip/clk-rk3368.c | |
| parent | 0cd74eec54a3ec34416bab6cc640a88230472078 (diff) | |
clk: rockchip: support more core div setting
Use arrays to support more core independent div settings.
A55 supports each core to work at different frequencies, and each core
has an independent divider control.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210315085608.16010-4-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3368.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3368.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 9a0dab9448db..2c50cc2cc6db 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -154,9 +154,10 @@ static struct clk_div_table div_ddrphy_t[] = { #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = { - .core_reg = RK3368_CLKSEL_CON(0), - .div_core_shift = 0, - .div_core_mask = 0x1f, + .core_reg[0] = RK3368_CLKSEL_CON(0), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .num_cores = 1, .mux_core_alt = 1, .mux_core_main = 0, .mux_core_shift = 7, @@ -164,11 +165,12 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = { }; static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = { - .core_reg = RK3368_CLKSEL_CON(2), - .div_core_shift = 0, + .core_reg[0] = RK3368_CLKSEL_CON(2), + .div_core_shift[0] = 0, .mux_core_alt = 1, + .num_cores = 1, .mux_core_main = 0, - .div_core_mask = 0x1f, + .div_core_mask[0] = 0x1f, .mux_core_shift = 7, .mux_core_mask = 0x1, }; |