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authorDerek Basehore <dbasehore@chromium.org>2018-03-13 13:37:19 -0700
committerHeiko Stuebner <heiko@sntech.de>2018-03-14 00:37:22 +0100
commit4ee3fd4abeca30d530fe67972f1964f7454259d6 (patch)
tree466579a6610cb0f25a0b836c27dad771367c36aa /drivers/clk/rockchip/clk-rk3399.c
parent60cf09e45fbcbbbb3162f02e0923a25ae7f5627e (diff)
clk: rockchip: Add 1.6GHz PLL rate for rk3399
We need this rate to generate 100, 200, and 228.57MHz from the same PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for an external display. Signed-off-by: Derek Basehore <dbasehore@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3399.c')
-rw-r--r--drivers/clk/rockchip/clk-rk3399.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 6847120b61cd..3e57c6eef93d 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -57,6 +57,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),