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author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2017-06-09 12:46:06 +0200 |
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committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2017-06-09 13:12:55 +0200 |
commit | 9842452acd3dae661f4430c4460edd1fc188377f (patch) | |
tree | c9bf32e40756b4a10421746496abb8944af26d6f /drivers/clk/samsung/clk-exynos-audss.c | |
parent | 8a9cf26e303f8b1a02d8bf62cd4671f6714aa2fe (diff) |
clk: samsung: exynos542x: Add EPLL rate table
A specific clock rate table is added for EPLL so it is possible
to set frequency of the EPLL output clock as multiple of various
audio sampling rates.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos-audss.c')
0 files changed, 0 insertions, 0 deletions