diff options
| author | Sam Protsenko <semen.protsenko@linaro.org> | 2023-02-22 22:19:33 -0600 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-03-06 16:55:26 +0100 |
| commit | 65bf1fbe784cafaa10906b1ba1402920c61f4a7e (patch) | |
| tree | aa9c43a1c5952c49430c846b9959f2becddfdfdb /drivers/clk/samsung/clk-exynos5420.c | |
| parent | 45dab81899800e0e2874f6c9e58b8b0343f33edf (diff) | |
clk: samsung: Don't pass reg_base to samsung_clk_register_pll()
Base address can be derived from context structure. Remove `base'
argument from samsung_clk_register_pll() and use `ctx->reg_base'
instead, as it's done in other clock registering functions.
No functional change.
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223041938.22732-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5420.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 27b1c5d56bb3..46cac4980be2 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1606,8 +1606,7 @@ static void __init exynos5x_clk_init(struct device_node *np, else exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; - samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), - reg_base); + samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls)); samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, ARRAY_SIZE(exynos5x_fixed_rate_clks)); samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, |