diff options
| author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2016-08-18 17:01:20 +0200 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2016-09-09 17:35:10 +0200 |
| commit | 1d9aa64c37f55d2c242f27a5788bf16a4f1578e4 (patch) | |
| tree | bd9badf5a6c809434eaf284fd2bd6fd6eb6ec214 /drivers/clk/samsung/clk-exynos5440.c | |
| parent | 0299042dca9689cdccfaaf00c5f64425c3ac360f (diff) | |
clk: samsung: Use common registration function for pll2550x
There is no such significant differences in pll2550x PLL type
to justify a separate registration function. This patch adapts
exynos5440 driver to use the common function and removes
samsung_clk_register_pll2550x().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5440.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5440.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c index a57d01b99b76..a80f3ef20801 100644 --- a/drivers/clk/samsung/clk-exynos5440.c +++ b/drivers/clk/samsung/clk-exynos5440.c @@ -112,6 +112,11 @@ static struct notifier_block exynos5440_clk_restart_handler = { .priority = 128, }; +static const struct samsung_pll_clock exynos5440_plls[] __initconst = { + PLL(pll_2550x, CLK_CPLLA, "cplla", "xtal", 0, 0x4c, NULL), + PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL), +}; + /* register exynos5440 clocks */ static void __init exynos5440_clk_init(struct device_node *np) { @@ -129,8 +134,8 @@ static void __init exynos5440_clk_init(struct device_node *np) samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks, ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); - samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10); - samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10); + samsung_clk_register_pll(ctx, exynos5440_plls, + ARRAY_SIZE(exynos5440_plls), ctx->reg_base); samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks, ARRAY_SIZE(exynos5440_fixed_rate_clks)); |