diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-07-07 12:26:13 -0700 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-07-07 12:26:13 -0700 |
commit | dddd564dbb5934c9a0c401491cafb98ab1c82fc6 (patch) | |
tree | 696aac5d6aa305420983133d45255a36c956cd8e /drivers/clk/samsung/clk-pll.c | |
parent | dd6ec12f3bf83ca3c4e712a9f35960aec779f6f9 (diff) | |
parent | 3cf50f6b13a2b2325532bc389107e6a2dcc99314 (diff) |
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This time we've got one core change to introduce a bulk clk_get API,
some new clk drivers and updates for old ones. The diff is pretty
spread out across a handful of different SoC clk drivers for Broadcom,
TI, Qualcomm, Renesas, Rockchip, Samsung, and Allwinner, mostly due to
the introduction of new drivers.
Core:
- New clk bulk get APIs
- Clk divider APIs gained the ability to consider a different parent
than the current one
New Drivers:
- Renesas r8a779{0,1,2,4} CPG/MSSR
- TI Keystone SCI firmware controlled clks and OMAP4 clkctrl
- Qualcomm IPQ8074 SoCs
- Cortina Systems Gemini (SL3516/CS3516)
- Rockchip rk3128 SoCs
- Allwinner A83T clk control units
- Broadcom Stingray SoCs
- CPU clks for Mediatek MT8173/MT2701/MT7623 SoCs
Removed Drivers:
- Old non-DT version of the Realview clk driver
Updates:
- Renesas Kconfig/Makefile cleanups
- Amlogic CEC EE clk support
- Improved Armada 7K/8K cp110 clk support
- Rockchip clk id exposing, critical clk markings
- Samsung converted to clk_hw registration APIs
- Fixes for Samsung exynos5420 audio clks
- USB2 clks for Hisilicon hi3798cv200 SoC and video/camera clks for
hi3660"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (147 commits)
clk: gemini: Read status before using the value
clk: scpi: error when clock fails to register
clk: at91: Add sama5d2 suspend/resume
gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K
clk: keystone: TI_SCI_PROTOCOL is needed for clk driver
clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLL
clk: uniphier: provide NAND controller clock rate
clk: hisilicon: add usb2 clocks for hi3798cv200 SoC
clk: Add Gemini SoC clock controller
clk: iproc: Remove __init marking on iproc_pll_clk_setup()
clk: bcm: Add clocks for Stingray SOC
dt-bindings: clk: Extend binding doc for Stingray SOC
clk: mediatek: export cpu multiplexer clock for MT8173 SoCs
clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs
clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work
clk: renesas: cpg-mssr: Use of_device_get_match_data() helper
clk: hi6220: add acpu clock
clk: zx296718: export I2S mux clocks
clk: imx7d: create clocks behind rawnand clock gate
clk: hi3660: Set PPLL2 to 2880M
...
Diffstat (limited to 'drivers/clk/samsung/clk-pll.c')
-rw-r--r-- | drivers/clk/samsung/clk-pll.c | 101 |
1 files changed, 57 insertions, 44 deletions
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 52290894857a..037c61484098 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -23,6 +23,10 @@ struct samsung_clk_pll { struct clk_hw hw; void __iomem *lock_reg; void __iomem *con_reg; + /* PLL enable control bit offset in @con_reg register */ + unsigned short enable_offs; + /* PLL lock status bit offset in @con_reg register */ + unsigned short lock_offs; enum samsung_pll_type type; unsigned int rate_count; const struct samsung_pll_rate_table *rate_table; @@ -61,6 +65,34 @@ static long samsung_pll_round_rate(struct clk_hw *hw, return rate_table[i - 1].rate; } +static int samsung_pll3xxx_enable(struct clk_hw *hw) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp; + + tmp = readl_relaxed(pll->con_reg); + tmp |= BIT(pll->enable_offs); + writel_relaxed(tmp, pll->con_reg); + + /* wait lock time */ + do { + cpu_relax(); + tmp = readl_relaxed(pll->con_reg); + } while (!(tmp & BIT(pll->lock_offs))); + + return 0; +} + +static void samsung_pll3xxx_disable(struct clk_hw *hw) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp; + + tmp = readl_relaxed(pll->con_reg); + tmp &= ~BIT(pll->enable_offs); + writel_relaxed(tmp, pll->con_reg); +} + /* * PLL2126 Clock Type */ @@ -142,34 +174,6 @@ static const struct clk_ops samsung_pll3000_clk_ops = { #define PLL35XX_LOCK_STAT_SHIFT (29) #define PLL35XX_ENABLE_SHIFT (31) -static int samsung_pll35xx_enable(struct clk_hw *hw) -{ - struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 tmp; - - tmp = readl_relaxed(pll->con_reg); - tmp |= BIT(PLL35XX_ENABLE_SHIFT); - writel_relaxed(tmp, pll->con_reg); - - /* wait_lock_time */ - do { - cpu_relax(); - tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT))); - - return 0; -} - -static void samsung_pll35xx_disable(struct clk_hw *hw) -{ - struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 tmp; - - tmp = readl_relaxed(pll->con_reg); - tmp &= ~BIT(PLL35XX_ENABLE_SHIFT); - writel_relaxed(tmp, pll->con_reg); -} - static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -238,12 +242,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, (rate->sdiv << PLL35XX_SDIV_SHIFT); writel_relaxed(tmp, pll->con_reg); - /* wait_lock_time if enabled */ - if (tmp & BIT(PLL35XX_ENABLE_SHIFT)) { + /* Wait until the PLL is locked if it is enabled. */ + if (tmp & BIT(pll->enable_offs)) { do { cpu_relax(); tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT))); + } while (!(tmp & BIT(pll->lock_offs))); } return 0; } @@ -252,8 +256,8 @@ static const struct clk_ops samsung_pll35xx_clk_ops = { .recalc_rate = samsung_pll35xx_recalc_rate, .round_rate = samsung_pll_round_rate, .set_rate = samsung_pll35xx_set_rate, - .enable = samsung_pll35xx_enable, - .disable = samsung_pll35xx_disable, + .enable = samsung_pll3xxx_enable, + .disable = samsung_pll3xxx_disable, }; static const struct clk_ops samsung_pll35xx_clk_min_ops = { @@ -275,6 +279,7 @@ static const struct clk_ops samsung_pll35xx_clk_min_ops = { #define PLL36XX_SDIV_SHIFT (0) #define PLL36XX_KDIV_SHIFT (0) #define PLL36XX_LOCK_STAT_SHIFT (29) +#define PLL36XX_ENABLE_SHIFT (31) static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -354,10 +359,12 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(pll_con1, pll->con_reg + 4); /* wait_lock_time */ - do { - cpu_relax(); - tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT))); + if (pll_con0 & BIT(pll->enable_offs)) { + do { + cpu_relax(); + tmp = readl_relaxed(pll->con_reg); + } while (!(tmp & BIT(pll->lock_offs))); + } return 0; } @@ -366,6 +373,8 @@ static const struct clk_ops samsung_pll36xx_clk_ops = { .recalc_rate = samsung_pll36xx_recalc_rate, .set_rate = samsung_pll36xx_set_rate, .round_rate = samsung_pll_round_rate, + .enable = samsung_pll3xxx_enable, + .disable = samsung_pll3xxx_disable, }; static const struct clk_ops samsung_pll36xx_clk_min_ops = { @@ -1244,7 +1253,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, void __iomem *base) { struct samsung_clk_pll *pll; - struct clk *clk; struct clk_init_data init; int ret, len; @@ -1288,6 +1296,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_1450x: case pll_1451x: case pll_1452x: + pll->enable_offs = PLL35XX_ENABLE_SHIFT; + pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; if (!pll->rate_table) init.ops = &samsung_pll35xx_clk_min_ops; else @@ -1306,6 +1316,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, /* clk_ops for 36xx and 2650 are similar */ case pll_36xx: case pll_2650: + pll->enable_offs = PLL36XX_ENABLE_SHIFT; + pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; if (!pll->rate_table) init.ops = &samsung_pll36xx_clk_min_ops; else @@ -1376,20 +1388,21 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, pll->lock_reg = base + pll_clk->lock_offset; pll->con_reg = base + pll_clk->con_offset; - clk = clk_register(NULL, &pll->hw); - if (IS_ERR(clk)) { - pr_err("%s: failed to register pll clock %s : %ld\n", - __func__, pll_clk->name, PTR_ERR(clk)); + ret = clk_hw_register(NULL, &pll->hw); + if (ret) { + pr_err("%s: failed to register pll clock %s : %d\n", + __func__, pll_clk->name, ret); kfree(pll); return; } - samsung_clk_add_lookup(ctx, clk, pll_clk->id); + samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); if (!pll_clk->alias) return; - ret = clk_register_clkdev(clk, pll_clk->alias, pll_clk->dev_name); + ret = clk_hw_register_clkdev(&pll->hw, pll_clk->alias, + pll_clk->dev_name); if (ret) pr_err("%s: failed to register lookup for %s : %d", __func__, pll_clk->name, ret); |