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| author | Stephen Boyd <sboyd@kernel.org> | 2020-09-21 13:49:11 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-09-21 13:49:11 -0700 |
| commit | 7aa908b48d6e8dae468022429166030d8b609ba5 (patch) | |
| tree | 3e85967eb6138654277207cbd5e437e4bc253780 /drivers/clk/socfpga/clk-agilex.c | |
| parent | 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 (diff) | |
| parent | 15d683e61bdded719e6202fed2c7401f4dcd95ab (diff) | |
Merge tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the new R-Car V3U (R8A779A0) SoC
- Add support for the VSP for Resizing clock on RZ/G1H,
- Fix VSP clock names to match corrected hardware documentation.
- Minor fixes and improvements
* tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3: Update description for RZ/G2
clk: renesas: cpg-mssr: Add support for R-Car V3U
clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779a0 SYSC power domain definitions
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
clk: renesas: r8a7742: Add clk entry for VSPR
Diffstat (limited to 'drivers/clk/socfpga/clk-agilex.c')
0 files changed, 0 insertions, 0 deletions