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authorMaxime Ripard <maxime.ripard@free-electrons.com>2016-11-08 18:12:34 +0100
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-01-23 11:44:27 +0100
commite66f81bbd7464621215219b72a0523f1b1078fae (patch)
tree92a3d993ca4999754bc512a66a3830577bde95d3 /drivers/clk/sunxi-ng/ccu_nkm.c
parentd77e8135b3405dd08a6bf05613d765cbd0bfd5a6 (diff)
clk: sunxi-ng: Implement factors offsets
The factors we've seen so far all had an offset of one. However, on the earlier Allwinner SoCs, some factors could have no offset at all, meaning that the value computed to reach the rate we want to use was the one we had to program in the registers. Implement an additional field for the factors that can have such an offset (linears, not based on a power of two) to specify that offset. This offset is not linked to the extremums that can be specified in those structures too. The minimum and maximum are representing the range of values we can use to try to compute the best rate. The offset comes later on when we want to set the best value in the registers. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_nkm.c')
-rw-r--r--drivers/clk/sunxi-ng/ccu_nkm.c18
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index 9b840a47a94d..3caaf9d603e2 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -82,14 +82,23 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
n = reg >> nkm->n.shift;
n &= (1 << nkm->n.width) - 1;
+ n += nkm->n.offset;
+ if (!n)
+ n++;
k = reg >> nkm->k.shift;
k &= (1 << nkm->k.width) - 1;
+ k += nkm->k.offset;
+ if (!k)
+ k++;
m = reg >> nkm->m.shift;
m &= (1 << nkm->m.width) - 1;
+ m += nkm->m.offset;
+ if (!m)
+ m++;
- return parent_rate * (n + 1) * (k + 1) / (m + 1);
+ return parent_rate * n * k / m;
}
static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
@@ -145,10 +154,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift);
reg &= ~GENMASK(nkm->m.width + nkm->m.shift - 1, nkm->m.shift);
- reg |= (_nkm.n - 1) << nkm->n.shift;
- reg |= (_nkm.k - 1) << nkm->k.shift;
- reg |= (_nkm.m - 1) << nkm->m.shift;
-
+ reg |= (_nkm.n - nkm->n.offset) << nkm->n.shift;
+ reg |= (_nkm.k - nkm->k.offset) << nkm->k.shift;
+ reg |= (_nkm.m - nkm->m.offset) << nkm->m.shift;
writel(reg, nkm->common.base + nkm->common.reg);
spin_unlock_irqrestore(nkm->common.lock, flags);