diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2019-03-14 19:21:08 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-03-18 08:07:21 +0100 |
| commit | 6630aad719bc0a46dcc4a6732ab783c4c9b80f88 (patch) | |
| tree | 5dc7bad92780d824727d649d60222487c28b9096 /drivers/clk/sunxi/Kconfig | |
| parent | ab65e04dc101d55f1509059725cf9d331141f6e8 (diff) | |
clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.
Fix this problem.
Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/clk/sunxi/Kconfig')
0 files changed, 0 insertions, 0 deletions