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authorEmilio López <emilio@elopez.com.ar>2014-07-18 15:28:02 -0300
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-10-21 21:51:29 +0200
commit9b038bc58ad2658c76fd8b50bb333dfd4454573c (patch)
tree00ea3d70e94441ae7b7a0fd43b1f4c2e083d651a /drivers/clk/sunxi/Makefile
parente2771545f49fbfec874642533058a3423fa29e16 (diff)
clk: sunxi: mod1 clock support
The module 1 type of clocks consist of a gate and a mux and are used on the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or SPDIF. This commit adds support for them on the sunxi clock driver. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'drivers/clk/sunxi/Makefile')
-rw-r--r--drivers/clk/sunxi/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 70a449a419e6..cb4c299214ce 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -5,6 +5,7 @@
obj-y += clk-sunxi.o clk-factors.o
obj-y += clk-a10-codec.o
obj-y += clk-a10-hosc.o
+obj-y += clk-a10-mod1.o
obj-y += clk-a10-pll2.o
obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o