diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2019-02-15 17:30:13 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2019-02-15 17:31:41 +0100 |
| commit | 7e5c4c26c7feefd3f3d9110744ba0bf6ab41ac2a (patch) | |
| tree | 9eea4e82a20712a2dcd2daea853f4e6f8523bd41 /drivers/clk/tegra/clk-dfll.h | |
| parent | f35635a6b769a63cae7e9c1a1f6cff7e1700584a (diff) | |
| parent | 8bf9437a4e7f7c97909c6ace50cdd1177b907853 (diff) | |
Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
clk: tegra: Changes for v5.1-rc1
This contains a couple of prerequisite patches to enable CPU frequency
scaling on Tegra210.
* tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
clk: tegra: dfll: add CVB tables for Tegra210
clk: tegra: dfll: round down voltages based on alignment
clk: tegra: dfll: support PWM regulator control
clk: tegra: dfll: CVB calculation alignment with the regulator
clk: tegra: dfll: registration for multiple SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/clk/tegra/clk-dfll.h')
| -rw-r--r-- | drivers/clk/tegra/clk-dfll.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index 83352c8078f2..85d0d95223f3 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -1,6 +1,6 @@ /* * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver - * Copyright (C) 2013 NVIDIA Corporation. All rights reserved. + * Copyright (C) 2013-2019 NVIDIA Corporation. All rights reserved. * * Aleksandr Frid <afrid@nvidia.com> * Paul Walmsley <pwalmsley@nvidia.com> @@ -22,11 +22,14 @@ #include <linux/reset.h> #include <linux/types.h> +#include "cvb.h" + /** * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver * @dev: struct device * that holds the OPP table for the DFLL * @max_freq: maximum frequency supported on this SoC * @cvb: CPU frequency table for this SoC + * @alignment: parameters of the regulator step and offset * @init_clock_trimmers: callback to initialize clock trimmers * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage @@ -35,6 +38,7 @@ struct tegra_dfll_soc_data { struct device *dev; unsigned long max_freq; const struct cvb_table *cvb; + struct rail_alignment alignment; void (*init_clock_trimmers)(void); void (*set_clock_trimmers_high)(void); |