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authorPeter De Schrijver <pdeschrijver@nvidia.com>2013-08-22 18:44:06 +0300
committerPeter De Schrijver <pdeschrijver@nvidia.com>2013-11-26 18:45:40 +0200
commitd5ff89a82a6d272d210db68a9487877682c94a24 (patch)
treec36ffdccfae461a88901eb3e470e7bea60eeb52f /drivers/clk/tegra/clk-periph.c
parent00c674e42c278e7af7b39b6c72dbbaa5e7ebd96c (diff)
clk: tegra: simplify periph clock data
This patch determines the register bank for clock enable/disable and reset based on the clock ID instead of hardcoding it in the tables describing the clocks. This results in less data to be maintained in the tables, making the code easier to understand. The full benefit of the change will be realized once also other clocktypes will be table based. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-periph.c')
-rw-r--r--drivers/clk/tegra/clk-periph.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index b2309d37a963..735b0243261c 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -178,6 +178,7 @@ static struct clk *_tegra_clk_register_periph(const char *name,
{
struct clk *clk;
struct clk_init_data init;
+ struct tegra_clk_periph_regs *bank;
init.name = name;
init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
@@ -185,12 +186,17 @@ static struct clk *_tegra_clk_register_periph(const char *name,
init.parent_names = parent_names;
init.num_parents = num_parents;
+ bank = get_reg_bank(periph->gate.clk_num);
+ if (!bank)
+ return ERR_PTR(-EINVAL);
+
/* Data in .init is copied by clk_register(), so stack variable OK */
periph->hw.init = &init;
periph->magic = TEGRA_CLK_PERIPH_MAGIC;
periph->mux.reg = clk_base + offset;
periph->divider.reg = div ? (clk_base + offset) : NULL;
periph->gate.clk_base = clk_base;
+ periph->gate.regs = bank;
clk = clk_register(NULL, &periph->hw);
if (IS_ERR(clk))