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authorThierry Reding <treding@nvidia.com>2015-04-08 16:48:26 +0200
committerThierry Reding <treding@nvidia.com>2016-04-28 12:41:46 +0200
commit07314fc108e195044c074f4b443974b5aaa2d5d7 (patch)
tree0a35cd6f1464968b08f384ed6d4ab093a31f4d5f /drivers/clk/tegra/clk-tegra-periph.c
parenta9caa8481258576b59b46067dfd8fd6fbd72f3e3 (diff)
clk: tegra: Special-case mipi-cal parent on Tegra114
Starting with Tegra124, the mipi-cal clock uses the 72 MHz clock as its source. On Tegra114 this clock's parent was clk_m, so it is the one-off chip. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra-periph.c')
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index b4e226a2f42c..463c114358e6 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -803,7 +803,7 @@ static struct tegra_periph_init_data gate_clks[] = {
GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
- GATE("mipi-cal", "clk_m", 56, 0, tegra_clk_mipi_cal, 0),
+ GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),