diff options
| author | Thierry Reding <treding@nvidia.com> | 2015-04-20 15:10:43 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:49 +0200 |
| commit | eede7113aabd3f40f8d9c32b1690f2859fcb101a (patch) | |
| tree | ffa6885caeb0e7e1a1e1a64161a4082771cceedc /drivers/clk/tegra/clk-tegra-periph.c | |
| parent | 98c4b3661b5aee0e583d17d6304f6489c0f41155 (diff) | |
clk: tegra: dpaux and dpaux1 are fixed factor clocks
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra-periph.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra-periph.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index c716b2885207..29d04c663abf 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -821,8 +821,6 @@ static struct tegra_periph_init_data gate_clks[] = { GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0), GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0), GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0), - GATE("dpaux", "pll_p", 181, 0, tegra_clk_dpaux, 0), - GATE("dpaux1", "pll_p", 207, 0, tegra_clk_dpaux1, 0), GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0), GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0), GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0), |