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authorPeter De Schrijver <pdeschrijver@nvidia.com>2017-07-25 13:34:09 +0300
committerStephen Boyd <sboyd@codeaurora.org>2017-08-23 15:59:42 -0700
commit3dd065e70e6c6ec54d2fc7d5158d88518d3c5ab9 (patch)
tree7238546e60d8885941db92b5b70f3196aa503587 /drivers/clk/tegra
parent82c875ca2b26fcca1a92ed4fd3a10bd653d6f680 (diff)
clk: tegra: change post IDDQ release delay to 5us
Increase delay after PLL IDDQ release to 5us per PLL specifications. based on work by Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/tegra')
-rw-r--r--drivers/clk/tegra/clk-pll.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 1c36b8a72bd2..695ccb436cec 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -363,7 +363,7 @@ static void _clk_pll_enable(struct clk_hw *hw)
val = pll_readl(pll->params->iddq_reg, pll);
val &= ~BIT(pll->params->iddq_bit_idx);
pll_writel(val, pll->params->iddq_reg, pll);
- udelay(2);
+ udelay(5);
}
if (pll->params->reset_reg) {