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| author | Chris Packham <chris.packham@alliedtelesis.co.nz> | 2018-05-24 17:23:41 +1200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-06-01 12:46:33 -0700 |
| commit | 00c5a926af12a9f0236928dab3dc9faf621406a1 (patch) | |
| tree | 50771e7c9a880b3c5c86574d173487e3d2a5e7de /drivers/clk/tegra | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
clk: mvebu: use correct bit for 98DX3236 NAND
The correct fieldbit value for the NAND PLL reload trigger is 27.
Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/tegra')
0 files changed, 0 insertions, 0 deletions