diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2017-10-04 02:02:39 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-11-01 15:00:04 +0100 |
| commit | 3ff46fd0b22abbb8d921d7e5657912bfbd41b6f0 (patch) | |
| tree | e2a7e4414151d8d37502ab06abbc5d28cabf482f /drivers/clk/tegra | |
| parent | 899f8095e66c562888ff617686e46019b758611b (diff) | |
clk: tegra: Correct parent of the APBDMA clock
APBDMA represents a clock gate to the APB DMA controller, the actual
clock source for the controller is PCLK.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra-periph.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index f5232d6d203d..c02711927d79 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -808,7 +808,7 @@ static struct tegra_periph_init_data gate_clks[] = { GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0), - GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), + GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0), GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), |