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authorKunihiko Hayashi <hayashi.kunihiko@socionext.com>2018-03-23 14:11:41 +0900
committerStephen Boyd <sboyd@kernel.org>2018-03-23 09:39:36 -0700
commitc2fd8756c5c3a3187094a4e7d7a6c87aa8033901 (patch)
tree17b96975379bfc830ddb50942740f0ed3425020e /drivers/clk/uniphier
parentafeb079bc8d8331a18c5371519279682f563f4bf (diff)
clk: uniphier: add ethernet clock control support for PXs3
Add clock control for ethernet controller on PXs3 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/uniphier')
-rw-r--r--drivers/clk/uniphier/clk-uniphier-sys.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 06c5269f63f5..fa7f2f3f8e36 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -244,6 +244,8 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
UNIPHIER_LD20_SYS_CLK_SD,
UNIPHIER_LD11_SYS_CLK_NAND(2),
UNIPHIER_LD11_SYS_CLK_EMMC(4),
+ UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
+ UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */
UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */
UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */