diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-06-29 22:39:03 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2020-07-09 11:37:43 +0200 |
| commit | e653b41131f60054dbfa0c7431613d6aeaee2212 (patch) | |
| tree | 036fc9a0082382573c4d94cbdcdebd50ecb6eb70 /drivers/clk/zynqmp | |
| parent | d4db5721f3c847df43b967d9f02994b15e4a48e6 (diff) | |
clk: meson: meson8b: add the vclk_en gate clock
HHI_VID_CLK_CNTL[19] is documented as CLK_EN0. This description is the
same in the public S912 datasheet and the GXBB driver calls this gate
"vclk". Add this gate clock to the Meson8/Meson8b/Meson8m2 clock
controller because it's needed to make the video output work.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200629203904.2989007-2-martin.blumenstingl@googlemail.com
Diffstat (limited to 'drivers/clk/zynqmp')
0 files changed, 0 insertions, 0 deletions