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authorEugen Hristev <eugen.hristev@microchip.com>2020-11-19 17:43:09 +0200
committerStephen Boyd <sboyd@kernel.org>2020-12-19 11:50:55 -0800
commit83d002877365afac2cb65ef4ad36b445652ebda3 (patch)
treede4f1b720675fb84b978060e62c5cb670762fe08 /drivers/clk
parent3d86ee17d4670406d07f92da6fa4f2aa82cdc5a2 (diff)
clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock from phandle in DT. Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea@microchip.com: adapt commit message, add CPU PLL] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/at91/sama7g5.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 7ef7963126b6..d3c3469d47d9 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -117,7 +117,8 @@ static const struct {
.p = "cpupll_fracck",
.l = &pll_layout_divpmc,
.t = PLL_TYPE_DIV,
- .c = 1, },
+ .c = 1,
+ .eid = PMC_CPUPLL, },
},
[PLL_ID_SYS] = {
@@ -131,7 +132,8 @@ static const struct {
.p = "syspll_fracck",
.l = &pll_layout_divpmc,
.t = PLL_TYPE_DIV,
- .c = 1, },
+ .c = 1,
+ .eid = PMC_SYSPLL, },
},
[PLL_ID_DDR] = {