Merge tag 'mmc-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC and MEMSTICK updates from Ulf Hansson:
 "MMC core:
   - A few minor improvements and cleanups

  MMC host:
   - Remove some redundant calls to local_irq_{save,restore}()
   - Replace kmap_atomic() with kmap_local_page()
   - Take return values from mmc_add_host() into account
   - dw_mmc-pltfm: Add support to configure clk-phase for socfpga
   - hsq: Minimize latency by using a fifo to dispatch requests
   - litex_mmc: Fixup corner case for polling mode
   - mtk-sd: Add inline crypto engine clock control
   - mtk-sd: Add support for the mediatek MT7986 variant
   - renesas_sdhi: Improve reset from HS400 mode
   - renesas_sdhi: Take DMA end interrupts into account
   - sdhci: Avoid unnecessary update of clock
   - sdhci: Fix an SD tuning issue
   - sdhci-brcmst: Add Kamal Dasu as maintainer for the Broadcom driver
   - sdhci-esdhc-imx: Improve tuning logic
   - sdhci-esdhc-imx: Improve support for the imxrt1050 variant
   - sdhci_f_sdh30: Add support for non-removable media
   - sdhci_f_sdh30: Add support for the Socionext F_SDH30_E51 variant
   - sdhci_f_sdh30: Add reset control support
   - sdhci-msm: Add support for the Qcom SM8550/SM8350/SM6375 variants
   - sdhci-msm: Add support for the Qcom MSM8976 variant
   - sdhci-of-arasan: Add support for dynamic configuration
   - sdhci-of-esdhc: Limit the clock frequency to confirm to spec
   - sdhci-pci: Enable asynchronous probe
   - sdhci-sprd: Improve card detection
   - sdhci-tegra: Improve reset support
   - sdhci-tegra: Add support to program MC stream ID
   - sunplus-mmc: Add new mmc driver for the Sunplus SP7021 controller
   - vub300: Fix warning splat for SDIO irq

  MEMSTICK core:
   - memstick: A few minor improvements and cleanups

  CLK/IOMMU:
   - clk: socfpga: Drop redundant support for clk-phase for the SD/MMC clk
   - iommu: Add tegra specific helper to get stream_id"

* tag 'mmc-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (108 commits)
  mmc: sdhci-sprd: Disable CLK_AUTO when the clock is less than 400K
  mmc: sdhci-of-esdhc: Modify mismatched function name
  memstick/mspro_block: Convert to use sysfs_emit()/sysfs_emit_at() APIs
  mmc: sdhci-tegra: Issue CMD and DAT resets together
  mmc: sdhci-tegra: Add support to program MC stream ID
  mmc: sdhci-tegra: Separate Tegra194 and Tegra234 SoC data
  mmc: sdhci-tegra: Sort includes alphabetically
  iommu/tegra: Add tegra_dev_iommu_get_stream_id() helper
  iommu: Add note about struct iommu_fwspec usage
  mmc: sdhci-brcmstb: Resolve "unused" warnings with CONFIG_OF=n
  dt-bindings: mmc: sdhci-msm: allow dma-coherent
  dt-bindings: mmc: sdhci-msm: drop properties mentioned in common MMC
  dt-bindings: mmc: sdhci-msm: cleanup style
  dt-bindings: mmc: sdhci-am654: cleanup style
  dt-bindings: mmc: sdhci: document sdhci-caps and sdhci-caps-mask
  mmc: vub300: fix warning - do not call blocking ops when !TASK_RUNNING
  MAINTAINERS: Update maintainer for SDHCI Broadcom BRCMSTB driver
  mmc: sdhci-of-esdhc: limit the SDHC clock frequency
  mmc: sdhci: Remove unneeded semicolon
  mmc: core: Normalize the error handling branch in sd_read_ext_regs()
  ...

3 files changed, 0 insertions, 130 deletions

diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index 738c53391e39..7cdf2f07c79b 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -35,59 +35,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
 	return parent_rate / div;
 }
 
-static int socfpga_clk_prepare(struct clk_hw *hwclk)
-{
-	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
-	int i;
-	u32 hs_timing;
-	u32 clk_phase[2];
-
-	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
-		for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
-			switch (socfpgaclk->clk_phase[i]) {
-			case 0:
-				clk_phase[i] = 0;
-				break;
-			case 45:
-				clk_phase[i] = 1;
-				break;
-			case 90:
-				clk_phase[i] = 2;
-				break;
-			case 135:
-				clk_phase[i] = 3;
-				break;
-			case 180:
-				clk_phase[i] = 4;
-				break;
-			case 225:
-				clk_phase[i] = 5;
-				break;
-			case 270:
-				clk_phase[i] = 6;
-				break;
-			case 315:
-				clk_phase[i] = 7;
-				break;
-			default:
-				clk_phase[i] = 0;
-				break;
-			}
-		}
-
-		hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
-		if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
-			regmap_write(socfpgaclk->sys_mgr_base_addr,
-				     SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
-		else
-			pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n",
-					__func__);
-	}
-	return 0;
-}
-
 static struct clk_ops gateclk_ops = {
-	.prepare = socfpga_clk_prepare,
 	.recalc_rate = socfpga_gate_clk_recalc_rate,
 };
 
@@ -96,7 +44,6 @@ static void __init __socfpga_gate_init(struct device_node *node,
 {
 	u32 clk_gate[2];
 	u32 div_reg[3];
-	u32 clk_phase[2];
 	u32 fixed_div;
 	struct clk_hw *hw_clk;
 	struct socfpga_gate_clk *socfpga_clk;
@@ -136,21 +83,6 @@ static void __init __socfpga_gate_init(struct device_node *node,
 		socfpga_clk->div_reg = NULL;
 	}
 
-	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
-	if (!rc) {
-		socfpga_clk->clk_phase[0] = clk_phase[0];
-		socfpga_clk->clk_phase[1] = clk_phase[1];
-
-		socfpga_clk->sys_mgr_base_addr =
-			syscon_regmap_lookup_by_compatible("altr,sys-mgr");
-		if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {
-			pr_err("%s: failed to find altr,sys-mgr regmap!\n",
-					__func__);
-			kfree(socfpga_clk);
-			return;
-		}
-	}
-
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
 	init.name = clk_name;
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 53d6e3ec4309..3e347b9e9eff 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -108,61 +108,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
 	return parent_rate / div;
 }
 
-static int socfpga_clk_prepare(struct clk_hw *hwclk)
-{
-	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
-	struct regmap *sys_mgr_base_addr;
-	int i;
-	u32 hs_timing;
-	u32 clk_phase[2];
-
-	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
-		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
-		if (IS_ERR(sys_mgr_base_addr)) {
-			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
-			return -EINVAL;
-		}
-
-		for (i = 0; i < 2; i++) {
-			switch (socfpgaclk->clk_phase[i]) {
-			case 0:
-				clk_phase[i] = 0;
-				break;
-			case 45:
-				clk_phase[i] = 1;
-				break;
-			case 90:
-				clk_phase[i] = 2;
-				break;
-			case 135:
-				clk_phase[i] = 3;
-				break;
-			case 180:
-				clk_phase[i] = 4;
-				break;
-			case 225:
-				clk_phase[i] = 5;
-				break;
-			case 270:
-				clk_phase[i] = 6;
-				break;
-			case 315:
-				clk_phase[i] = 7;
-				break;
-			default:
-				clk_phase[i] = 0;
-				break;
-			}
-		}
-		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
-		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
-			hs_timing);
-	}
-	return 0;
-}
-
 static struct clk_ops gateclk_ops = {
-	.prepare = socfpga_clk_prepare,
 	.recalc_rate = socfpga_clk_recalc_rate,
 	.get_parent = socfpga_clk_get_parent,
 	.set_parent = socfpga_clk_set_parent,
@@ -172,7 +118,6 @@ void __init socfpga_gate_init(struct device_node *node)
 {
 	u32 clk_gate[2];
 	u32 div_reg[3];
-	u32 clk_phase[2];
 	u32 fixed_div;
 	struct clk_hw *hw_clk;
 	struct socfpga_gate_clk *socfpga_clk;
@@ -218,12 +163,6 @@ void __init socfpga_gate_init(struct device_node *node)
 		socfpga_clk->div_reg = NULL;
 	}
 
-	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
-	if (!rc) {
-		socfpga_clk->clk_phase[0] = clk_phase[0];
-		socfpga_clk->clk_phase[1] = clk_phase[1];
-	}
-
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
 	init.name = clk_name;
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d80115fbdd6a..9a2fb2dde5b8 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -50,7 +50,6 @@ struct socfpga_gate_clk {
 	u32 width;	/* only valid if div_reg != 0 */
 	u32 shift;	/* only valid if div_reg != 0 */
 	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
-	u32 clk_phase[2];
 };
 
 struct socfpga_periph_clk {