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authorSylwester Nawrocki <s.nawrocki@samsung.com>2016-08-22 11:14:49 +0200
committerSylwester Nawrocki <s.nawrocki@samsung.com>2016-09-09 17:35:09 +0200
commit0299042dca9689cdccfaaf00c5f64425c3ac360f (patch)
treeb8e4cf997438db2a5c5946ab362a412fa503cc43 /drivers/clk
parente867e8fa825dd4fae2514883d77f5954d8d90991 (diff)
clk: samsung: exynos5410: Expose the peripheral DMA gate clocks
These clocks are needed in order to use the PL330 peripheral DMA controllers. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/samsung/clk-exynos5410.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index 5488a4460c15..eefed92a59aa 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -176,6 +176,8 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
+ GATE(CLK_PDMA1, "pdma1", "aclk200", GATE_BUS_FSYS0, 2, 0, 0),
+ GATE(CLK_PDMA0, "pdma0", "aclk200", GATE_BUS_FSYS0, 1, 0, 0),
GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),