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authorColin Ian King <colin.king@canonical.com>2021-06-29 11:29:56 +0100
committerStephen Boyd <sboyd@kernel.org>2021-06-30 11:19:15 -0700
commit2cdee50eda9d87f4fabba3df00caa4cc873f30ab (patch)
tree68b36b7ada3fe298d90e5df8fc219c6960ed8b6d /drivers/clk
parentb424f73b6c017f907fd4018bd109d62b237f7875 (diff)
clk: lmk04832: Fix spelling mistakes in dev_err messages and comments
There are handful of spelling mistakes in two dev_err error messages and comments. Fix them. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210629102956.17901-1-colin.king@canonical.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk-lmk04832.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c
index 246095b1ab45..c7a3a029fb1e 100644
--- a/drivers/clk/clk-lmk04832.c
+++ b/drivers/clk/clk-lmk04832.c
@@ -519,7 +519,7 @@ static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);
if (vco_rate < 0) {
- dev_err(lmk->dev, "PLL2 parmeters out of range\n");
+ dev_err(lmk->dev, "PLL2 parameters out of range\n");
return vco_rate;
}
@@ -550,7 +550,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
if (vco_rate < 0) {
- dev_err(lmk->dev, "failed to determine PLL2 parmeters\n");
+ dev_err(lmk->dev, "failed to determine PLL2 parameters\n");
return vco_rate;
}
@@ -573,7 +573,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
/*
* PLL2_N registers must be programmed after other PLL2 dividers are
- * programed to ensure proper VCO frequency calibration
+ * programmed to ensure proper VCO frequency calibration
*/
ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
FIELD_GET(0x030000, n));
@@ -1120,7 +1120,7 @@ static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
return -EINVAL;
}
- /* Enable Duty Cycle Corretion */
+ /* Enable Duty Cycle Correction */
if (dclk_div == 1) {
ret = regmap_update_bits(lmk->regmap,
LMK04832_REG_CLKOUT_CTRL3(dclk->id),