summaryrefslogtreecommitdiff
path: root/drivers/clk
diff options
context:
space:
mode:
authorArnd Bergmann <arnd@arndb.de>2013-04-09 15:10:50 +0200
committerArnd Bergmann <arnd@arndb.de>2013-04-09 15:10:50 +0200
commit6abb0576791c95cc7af259ea0372661e39439bde (patch)
tree7a9e832cc4111021d5a574d3e02b85eb85a4af6c /drivers/clk
parent8bd2bcf320cfd0e7118da61d186c8466a247ef62 (diff)
parenteebd1fda2342014a50ed3fd132e5dc6e8b5251e8 (diff)
Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/fixes-non-critical
From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: minor fixes This branch contains a variety of small build and run-time fixes that weren't important enough for 3.9. * Enable CPU errata WARs in secondary reset handler as a preparation for multi-platform support, and a related fix. * Don't touch DBLGAR in reset/resume handlers, so enable the code to run on A15 cores. * Minor build fixes. * A fix to the Tegra clock driver. * Some error-handling fixes. This branch is based on the previous fixes-for-mmc pull request. * tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: powergate: Don't error out if new state == old state ARM: tegra: Export tegra_powergate_sequence_power_up() memory: tegra30: Fix build error w/o PM ARM: tegra: fix ignored return value of regulator_enable ARM: tegra: fix the logical detection of power on sequence of warm boot CPUs ARM: tegra: Fix unchecked return value ARM: tegra: don't unlock MMIO access to DBGLAR clk: tegra: No 7.1 super clk dividers on Tegra20 ARM: tegra: remove save/restore of CPU diag register ARM: tegra: add CPU errata WARs to Tegra reset handler ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/clk-tegra20.c36
1 files changed, 2 insertions, 34 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 1e2de7305362..b92d48be4cc9 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -711,8 +711,8 @@ static void tegra20_pll_init(void)
}
static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
- "pll_p_cclk", "pll_p_out4_cclk",
- "pll_p_out3_cclk", "clk_d", "pll_x" };
+ "pll_p", "pll_p_out4",
+ "pll_p_out3", "clk_d", "pll_x" };
static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
"pll_p_out3", "pll_p_out2", "clk_d",
"clk_32k", "pll_m_out1" };
@@ -721,38 +721,6 @@ static void tegra20_super_clk_init(void)
{
struct clk *clk;
- /*
- * DIV_U71 dividers for CCLK, these dividers are used only
- * if parent clock is fixed rate.
- */
-
- /*
- * Clock input to cclk divided from pll_p using
- * U71 divider of cclk.
- */
- clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
- clk_base + SUPER_CCLK_DIVIDER, 0,
- TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
- clk_register_clkdev(clk, "pll_p_cclk", NULL);
-
- /*
- * Clock input to cclk divided from pll_p_out3 using
- * U71 divider of cclk.
- */
- clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
- clk_base + SUPER_CCLK_DIVIDER, 0,
- TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
- clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
-
- /*
- * Clock input to cclk divided from pll_p_out4 using
- * U71 divider of cclk.
- */
- clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
- clk_base + SUPER_CCLK_DIVIDER, 0,
- TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
- clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
-
/* CCLK */
clk = tegra_clk_register_super_mux("cclk", cclk_parents,
ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,