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authorStephen Boyd <sboyd@kernel.org>2021-06-29 13:33:16 -0700
committerStephen Boyd <sboyd@kernel.org>2021-06-29 13:33:16 -0700
commite51fbc55d3d3f68a9fb37c4e95c88404c4ff244c (patch)
treec5bb6799e315129ade4f0c7834388f543ef7bc55 /drivers/clk
parent029eae234be34e47a7bcde5c429c04d9e761ad07 (diff)
parent14de023dc0f752acad89e6932a96bdded479c60c (diff)
parent686f225039be2846845349669edbfc5771ba647a (diff)
parentfeb29cc744c1d4d503138708964f21840c23b3ea (diff)
parent03aea91bbe06d4ffae8c22c9e1e6671a76fd6d5a (diff)
parent99c6fc6d7ecb7961b33d6503a71c868bb4009478 (diff)
Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and 'clk-socfpga' into clk-next
* clk-rockchip: clk: rockchip: export ACLK_VCODEC for RK3036 clk: rockchip: fix rk3568 cpll clk gate bits clk: rockchip: Optimize PLL table memory usage * clk-amlogic: clk: meson: g12a: Add missing NNA source clocks for g12b clk: meson: axg-audio: improve deferral handling clk: meson: g12a: fix gp0 and hifi ranges clk: meson: pll: switch to determine_rate for the PLL ops * clk-yaml: dt-bindings: clock: gpio-mux-clock: Convert to json-schema * clk-zynq: clk: zynqmp: Handle divider specific read only flag clk: zynqmp: Use firmware specific mux clock flags clk: zynqmp: Use firmware specific divider clock flags clk: zynqmp: Use firmware specific common clock flags clk: zynqmp: pll: Remove some dead code clk: zynqmp: fix compile testing without ZYNQMP_FIRMWARE * clk-socfpga: clk: socfpga: clk-pll: Remove unused variable 'rc' clk: agilex/stratix10/n5x: fix how the bypass_reg is handled clk: agilex/stratix10: add support for the 2nd bypass clk: agilex/stratix10: fix bypass representation clk: agilex/stratix10: remove noc_clk