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authorRajan Vaja <rajan.vaja@xilinx.com>2019-12-04 22:35:55 -0800
committerStephen Boyd <sboyd@kernel.org>2020-01-23 13:22:44 -0800
commitc1e846b8ee5eee78765242fe204f566596c52ad1 (patch)
tree1e368fa197bb2098b98c1401263293ed58a1b2b6 /drivers/clk
parent352546805a44871b68affea09a2fbd5a48e452d0 (diff)
clk: zynqmp: Extend driver for versal
Add Versal compatible string to support Versal binding. Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lkml.kernel.org/r/1575527759-26452-3-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/zynqmp/clkc.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index a11f93ecbf34..10e89f23880b 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC clock controller
*
- * Copyright (C) 2016-2018 Xilinx
+ * Copyright (C) 2016-2019 Xilinx
*
* Based on drivers/clk/zynq/clkc.c
*/
@@ -749,6 +749,7 @@ static int zynqmp_clock_probe(struct platform_device *pdev)
static const struct of_device_id zynqmp_clock_of_match[] = {
{.compatible = "xlnx,zynqmp-clk"},
+ {.compatible = "xlnx,versal-clk"},
{},
};
MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);