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authorLey Foon Tan <leyfoon.tan@starfivetech.com>2024-03-07 01:23:30 +0800
committerDaniel Lezcano <daniel.lezcano@linaro.org>2024-03-13 12:08:59 +0100
commit8248ca30ef89f9cc74ace62ae1b9a22b5f16736c (patch)
tree6c773ccc00cdb6cbd2a49e64a9b282776e245c3e /drivers/clocksource
parentc819dbd078321f948101ef7a19f1e171164bb3cf (diff)
clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization
In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value. Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") Cc: <stable@vger.kernel.org> Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20240306172330.255844-1-leyfoon.tan@starfivetech.com
Diffstat (limited to 'drivers/clocksource')
-rw-r--r--drivers/clocksource/timer-riscv.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index e66dcbd66566..79bb9a98baa7 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -108,6 +108,9 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
{
struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
+ /* Clear timer interrupt */
+ riscv_clock_event_stop();
+
ce->cpumask = cpumask_of(cpu);
ce->irq = riscv_clock_event_irq;
if (riscv_timer_cannot_wake_cpu)