diff options
| author | Weili Qian <qianweili@huawei.com> | 2021-05-15 18:44:39 +0800 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2021-05-23 08:52:41 +0800 |
| commit | 3b9c24dec891d418e26032709d6f01fe3757a4a6 (patch) | |
| tree | 7ed93093448d064200a9876f9aad2ff4eb883153 /drivers/crypto/hisilicon/zip | |
| parent | 3121f021c00aeed599d6f5d1c737b1bc8e6a05d8 (diff) | |
crypto: hisilicon/qm - adjust order of device error configuration
In order to avoid reporting an exception but the error type is not
configured, the driver needs to configure the error type first, and then
enable the error interrupt. Before executing the task, hardware error
initialization is needed so that the hardware can detect the error in time.
Signed-off-by: Weili Qian <qianweili@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/hisilicon/zip')
| -rw-r--r-- | drivers/crypto/hisilicon/zip/zip_main.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c index 2178b40e9f82..8e3a52218774 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -333,13 +333,13 @@ static void hisi_zip_hw_error_enable(struct hisi_qm *qm) writel(HZIP_CORE_INT_RAS_NFE_ENABLE, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); - /* enable ZIP hw error interrupts */ - writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); - /* enable ZIP block master OOO when m-bit error occur */ val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); val = val | HZIP_AXI_SHUTDOWN_ENABLE; writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); + + /* enable ZIP hw error interrupts */ + writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); } static void hisi_zip_hw_error_disable(struct hisi_qm *qm) |