diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2021-02-16 20:09:52 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-02-16 20:36:38 -0800 |
| commit | b39cb1052a5cf41bc12201ec1c0ddae5cb8be868 (patch) | |
| tree | 13079eddea29561e8e20cd7f388e143ec97494ca /drivers/cxl/Makefile | |
| parent | 8adaf747c9f0b470aea1b0c88583aa0a344e1540 (diff) | |
cxl/mem: Register CXL memX devices
Create the /sys/bus/cxl hierarchy to enumerate:
* Memory Devices (per-endpoint control devices)
* Memory Address Space Devices (platform address ranges with
interleaving, performance, and persistence attributes)
* Memory Regions (active provisioned memory from an address space device
that is in use as System RAM or delegated to libnvdimm as Persistent
Memory regions).
For now, only the per-endpoint control devices are registered on the
'cxl' bus. However, going forward it will provide a mechanism to
coordinate cross-device interleave.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> (v2)
Link: https://lore.kernel.org/r/20210217040958.1354670-4-ben.widawsky@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/Makefile')
| -rw-r--r-- | drivers/cxl/Makefile | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index 4a30f7c3fc4a..a314a1891f4d 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_CXL_BUS) += cxl_bus.o obj-$(CONFIG_CXL_MEM) += cxl_mem.o +ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL +cxl_bus-y := bus.o cxl_mem-y := mem.o |