diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2022-11-29 10:48:48 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-03 13:40:17 -0800 |
| commit | bd09626b39dff97779e1543e25e60ab2876e7e88 (patch) | |
| tree | 42ddd99d1cf5e1a99be5eff8186f746a54d5032e /drivers/cxl/core/regs.c | |
| parent | a1554e9cac5ea04aaf2fb2de0df9936a94cb96fc (diff) | |
cxl/pci: Find and map the RAS Capability Structure
The RAS Capability Structure has some ancillary information that may be
relevant with respect to AER events, link and protcol error status
registers. Map the RAS Capability Registers in support of defining a
'struct pci_error_handlers' instance for the cxl_pci driver.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/166974412803.1608150.7096566580400947001.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/core/regs.c')
| -rw-r--r-- | drivers/cxl/core/regs.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 97e8f4201493..b10f8b79ec40 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -83,6 +83,12 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, rmap = &map->hdm_decoder; break; } + case CXL_CM_CAP_CAP_ID_RAS: + dev_dbg(dev, "found RAS capability (0x%x)\n", + offset); + length = CXL_RAS_CAPABILITY_LENGTH; + rmap = &map->ras; + break; default: dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id, offset); @@ -196,6 +202,7 @@ int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs, void __iomem **addr; } mapinfo[] = { { &map->component_map.hdm_decoder, ®s->hdm_decoder }, + { &map->component_map.ras, ®s->ras }, }; int i; |