diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2021-02-16 20:09:52 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-02-16 20:36:38 -0800 |
| commit | b39cb1052a5cf41bc12201ec1c0ddae5cb8be868 (patch) | |
| tree | 13079eddea29561e8e20cd7f388e143ec97494ca /drivers/cxl/cxl.h | |
| parent | 8adaf747c9f0b470aea1b0c88583aa0a344e1540 (diff) | |
cxl/mem: Register CXL memX devices
Create the /sys/bus/cxl hierarchy to enumerate:
* Memory Devices (per-endpoint control devices)
* Memory Address Space Devices (platform address ranges with
interleaving, performance, and persistence attributes)
* Memory Regions (active provisioned memory from an address space device
that is in use as System RAM or delegated to libnvdimm as Persistent
Memory regions).
For now, only the per-endpoint control devices are registered on the
'cxl' bus. However, going forward it will provide a mechanism to
coordinate cross-device interleave.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> (v2)
Link: https://lore.kernel.org/r/20210217040958.1354670-4-ben.widawsky@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxl.h')
| -rw-r--r-- | drivers/cxl/cxl.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index baac26d9e63b..8fd4a177fe25 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -57,6 +57,7 @@ (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ CXLMDEV_RESET_NEEDED_NOT) +struct cxl_memdev; /** * struct cxl_mem - A CXL memory device * @pdev: The PCI device associated with this CXL device. @@ -74,6 +75,7 @@ struct cxl_mem { struct pci_dev *pdev; void __iomem *regs; + struct cxl_memdev *cxlmd; void __iomem *status_regs; void __iomem *mbox_regs; @@ -87,4 +89,5 @@ struct cxl_mem { struct range ram_range; }; +extern struct bus_type cxl_bus_type; #endif /* __CXL_H__ */ |