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authorYazen Ghannam <Yazen.Ghannam@amd.com>2016-11-28 08:50:21 -0600
committerBorislav Petkov <bp@suse.de>2016-11-29 17:16:09 +0100
commit07ed82ef93d6c70dcd1f31429a8fd12fbdeb21fd (patch)
treeece4b6d863af47bea856721ac091a645dcc06ea2 /drivers/edac/amd64_edac.h
parent8051c0af3c846937d5454766fe407b08a7681256 (diff)
EDAC, amd64: Add Fam17h debug output
Read a few more UMC registers and provide debug output in order to be as similar as possible to older AMD systems. Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com> Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1480344621-14966-1-git-send-email-Yazen.Ghannam@amd.com [ Remove unneeded K8 check and comments, fixup others. ] Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'drivers/edac/amd64_edac.h')
-rw-r--r--drivers/edac/amd64_edac.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 34d915782d4a..cb91d0b06d23 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -260,9 +260,13 @@
/* UMC CH register offsets */
#define UMCCH_BASE_ADDR 0x0
#define UMCCH_ADDR_MASK 0x20
+#define UMCCH_ADDR_CFG 0x30
#define UMCCH_DIMM_CFG 0x80
+#define UMCCH_UMC_CFG 0x100
#define UMCCH_SDP_CTRL 0x104
#define UMCCH_ECC_CTRL 0x14C
+#define UMCCH_ECC_BAD_SYMBOL 0xD90
+#define UMCCH_UMC_CAP 0xDF0
#define UMCCH_UMC_CAP_HI 0xDF4
/* UMC CH bitfields */
@@ -316,8 +320,10 @@ struct chip_select {
struct amd64_umc {
u32 dimm_cfg; /* DIMM Configuration reg */
+ u32 umc_cfg; /* Configuration reg */
u32 sdp_ctrl; /* SDP Control reg */
u32 ecc_ctrl; /* DRAM ECC Control reg */
+ u32 umc_cap_hi; /* Capabilities High reg */
};
struct amd64_pvt {