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authorLinus Torvalds <torvalds@linux-foundation.org>2018-04-02 20:20:12 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2018-04-02 20:20:12 -0700
commitf5a8eb632b562bd9c16c389f5db3a5260fba4157 (patch)
tree82687234d772ff8f72a31e598fe16553885c56c9 /drivers/edac
parentc9297d284126b80c9cfd72c690e0da531c99fc48 (diff)
parentdd3b8c329aa270027fba61a02a12600972dc3983 (diff)
Merge tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pul removal of obsolete architecture ports from Arnd Bergmann: "This removes the entire architecture code for blackfin, cris, frv, m32r, metag, mn10300, score, and tile, including the associated device drivers. I have been working with the (former) maintainers for each one to ensure that my interpretation was right and the code is definitely unused in mainline kernels. Many had fond memories of working on the respective ports to start with and getting them included in upstream, but also saw no point in keeping the port alive without any users. In the end, it seems that while the eight architectures are extremely different, they all suffered the same fate: There was one company in charge of an SoC line, a CPU microarchitecture and a software ecosystem, which was more costly than licensing newer off-the-shelf CPU cores from a third party (typically ARM, MIPS, or RISC-V). It seems that all the SoC product lines are still around, but have not used the custom CPU architectures for several years at this point. In contrast, CPU instruction sets that remain popular and have actively maintained kernel ports tend to all be used across multiple licensees. [ See the new nds32 port merged in the previous commit for the next generation of "one company in charge of an SoC line, a CPU microarchitecture and a software ecosystem" - Linus ] The removal came out of a discussion that is now documented at https://lwn.net/Articles/748074/. Unlike the original plans, I'm not marking any ports as deprecated but remove them all at once after I made sure that they are all unused. Some architectures (notably tile, mn10300, and blackfin) are still being shipped in products with old kernels, but those products will never be updated to newer kernel releases. After this series, we still have a few architectures without mainline gcc support: - unicore32 and hexagon both have very outdated gcc releases, but the maintainers promised to work on providing something newer. At least in case of hexagon, this will only be llvm, not gcc. - openrisc, risc-v and nds32 are still in the process of finishing their support or getting it added to mainline gcc in the first place. They all have patched gcc-7.3 ports that work to some degree, but complete upstream support won't happen before gcc-8.1. Csky posted their first kernel patch set last week, their situation will be similar [ Palmer Dabbelt points out that RISC-V support is in mainline gcc since gcc-7, although gcc-7.3.0 is the recommended minimum - Linus ]" This really says it all: 2498 files changed, 95 insertions(+), 467668 deletions(-) * tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (74 commits) MAINTAINERS: UNICORE32: Change email account staging: iio: remove iio-trig-bfin-timer driver tty: hvc: remove tile driver tty: remove bfin_jtag_comm and hvc_bfin_jtag drivers serial: remove tile uart driver serial: remove m32r_sio driver serial: remove blackfin drivers serial: remove cris/etrax uart drivers usb: Remove Blackfin references in USB support usb: isp1362: remove blackfin arch glue usb: musb: remove blackfin port usb: host: remove tilegx platform glue pwm: remove pwm-bfin driver i2c: remove bfin-twi driver spi: remove blackfin related host drivers watchdog: remove bfin_wdt driver can: remove bfin_can driver mmc: remove bfin_sdh driver input: misc: remove blackfin rotary driver input: keyboard: remove bf54x driver ...
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/Kconfig8
-rw-r--r--drivers/edac/Makefile2
-rw-r--r--drivers/edac/tile_edac.c265
3 files changed, 0 insertions, 275 deletions
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 3c4017007647..cfcb91056f23 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -317,14 +317,6 @@ config EDAC_CPC925
a companion chip to the PowerPC 970 family of
processors.
-config EDAC_TILE
- tristate "Tilera Memory Controller"
- depends on TILE
- default y
- help
- Support for error detection and correction on the
- Tilera memory controller.
-
config EDAC_HIGHBANK_MC
tristate "Highbank Memory Controller"
depends on ARCH_HIGHBANK
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index b54912eb39af..02b43a7d8c3e 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,8 +64,6 @@ obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
obj-$(CONFIG_EDAC_AMD8111) += amd8111_edac.o
obj-$(CONFIG_EDAC_AMD8131) += amd8131_edac.o
-obj-$(CONFIG_EDAC_TILE) += tile_edac.o
-
obj-$(CONFIG_EDAC_HIGHBANK_MC) += highbank_mc_edac.o
obj-$(CONFIG_EDAC_HIGHBANK_L2) += highbank_l2_edac.o
diff --git a/drivers/edac/tile_edac.c b/drivers/edac/tile_edac.c
deleted file mode 100644
index 8a33a87e67f1..000000000000
--- a/drivers/edac/tile_edac.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- * Tilera-specific EDAC driver.
- *
- * This source code is derived from the following driver:
- *
- * Cell MIC driver for ECC counting
- *
- * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
- * <benh@kernel.crashing.org>
- *
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/uaccess.h>
-#include <linux/edac.h>
-#include <hv/hypervisor.h>
-#include <hv/drv_mshim_intf.h>
-
-#include "edac_module.h"
-
-#define DRV_NAME "tile-edac"
-
-/* Number of cs_rows needed per memory controller on TILEPro. */
-#define TILE_EDAC_NR_CSROWS 1
-
-/* Number of channels per memory controller on TILEPro. */
-#define TILE_EDAC_NR_CHANS 1
-
-/* Granularity of reported error in bytes on TILEPro. */
-#define TILE_EDAC_ERROR_GRAIN 8
-
-/* TILE processor has multiple independent memory controllers. */
-struct platform_device *mshim_pdev[TILE_MAX_MSHIMS];
-
-struct tile_edac_priv {
- int hv_devhdl; /* Hypervisor device handle. */
- int node; /* Memory controller instance #. */
- unsigned int ce_count; /*
- * Correctable-error counter
- * kept by the driver.
- */
-};
-
-static void tile_edac_check(struct mem_ctl_info *mci)
-{
- struct tile_edac_priv *priv = mci->pvt_info;
- struct mshim_mem_error mem_error;
-
- if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_error,
- sizeof(struct mshim_mem_error), MSHIM_MEM_ERROR_OFF) !=
- sizeof(struct mshim_mem_error)) {
- pr_err(DRV_NAME ": MSHIM_MEM_ERROR_OFF pread failure.\n");
- return;
- }
-
- /* Check if the current error count is different from the saved one. */
- if (mem_error.sbe_count != priv->ce_count) {
- dev_dbg(mci->pdev, "ECC CE err on node %d\n", priv->node);
- priv->ce_count = mem_error.sbe_count;
- edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
- 0, 0, 0,
- 0, 0, -1,
- mci->ctl_name, "");
- }
-}
-
-/*
- * Initialize the 'csrows' table within the mci control structure with the
- * addressing of memory.
- */
-static int tile_edac_init_csrows(struct mem_ctl_info *mci)
-{
- struct csrow_info *csrow = mci->csrows[0];
- struct tile_edac_priv *priv = mci->pvt_info;
- struct mshim_mem_info mem_info;
- struct dimm_info *dimm = csrow->channels[0]->dimm;
-
- if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_info,
- sizeof(struct mshim_mem_info), MSHIM_MEM_INFO_OFF) !=
- sizeof(struct mshim_mem_info)) {
- pr_err(DRV_NAME ": MSHIM_MEM_INFO_OFF pread failure.\n");
- return -1;
- }
-
- if (mem_info.mem_ecc)
- dimm->edac_mode = EDAC_SECDED;
- else
- dimm->edac_mode = EDAC_NONE;
- switch (mem_info.mem_type) {
- case DDR2:
- dimm->mtype = MEM_DDR2;
- break;
-
- case DDR3:
- dimm->mtype = MEM_DDR3;
- break;
-
- default:
- return -1;
- }
-
- dimm->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
- dimm->grain = TILE_EDAC_ERROR_GRAIN;
- dimm->dtype = DEV_UNKNOWN;
-
- return 0;
-}
-
-static int tile_edac_mc_probe(struct platform_device *pdev)
-{
- char hv_file[32];
- int hv_devhdl;
- struct mem_ctl_info *mci;
- struct edac_mc_layer layers[2];
- struct tile_edac_priv *priv;
- int rc;
-
- sprintf(hv_file, "mshim/%d", pdev->id);
- hv_devhdl = hv_dev_open((HV_VirtAddr)hv_file, 0);
- if (hv_devhdl < 0)
- return -EINVAL;
-
- /* A TILE MC has a single channel and one chip-select row. */
- layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
- layers[0].size = TILE_EDAC_NR_CSROWS;
- layers[0].is_virt_csrow = true;
- layers[1].type = EDAC_MC_LAYER_CHANNEL;
- layers[1].size = TILE_EDAC_NR_CHANS;
- layers[1].is_virt_csrow = false;
- mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,
- sizeof(struct tile_edac_priv));
- if (mci == NULL)
- return -ENOMEM;
- priv = mci->pvt_info;
- priv->node = pdev->id;
- priv->hv_devhdl = hv_devhdl;
-
- mci->pdev = &pdev->dev;
- mci->mtype_cap = MEM_FLAG_DDR2;
- mci->edac_ctl_cap = EDAC_FLAG_SECDED;
-
- mci->mod_name = DRV_NAME;
-#ifdef __tilegx__
- mci->ctl_name = "TILEGx_Memory_Controller";
-#else
- mci->ctl_name = "TILEPro_Memory_Controller";
-#endif
- mci->dev_name = dev_name(&pdev->dev);
- mci->edac_check = tile_edac_check;
-
- /*
- * Initialize the MC control structure 'csrows' table
- * with the mapping and control information.
- */
- if (tile_edac_init_csrows(mci)) {
- /* No csrows found. */
- mci->edac_cap = EDAC_FLAG_NONE;
- } else {
- mci->edac_cap = EDAC_FLAG_SECDED;
- }
-
- platform_set_drvdata(pdev, mci);
-
- /* Register with EDAC core */
- rc = edac_mc_add_mc(mci);
- if (rc) {
- dev_err(&pdev->dev, "failed to register with EDAC core\n");
- edac_mc_free(mci);
- return rc;
- }
-
- return 0;
-}
-
-static int tile_edac_mc_remove(struct platform_device *pdev)
-{
- struct mem_ctl_info *mci = platform_get_drvdata(pdev);
-
- edac_mc_del_mc(&pdev->dev);
- if (mci)
- edac_mc_free(mci);
- return 0;
-}
-
-static struct platform_driver tile_edac_mc_driver = {
- .driver = {
- .name = DRV_NAME,
- },
- .probe = tile_edac_mc_probe,
- .remove = tile_edac_mc_remove,
-};
-
-/*
- * Driver init routine.
- */
-static int __init tile_edac_init(void)
-{
- char hv_file[32];
- struct platform_device *pdev;
- int i, err, num = 0;
-
- /* Only support POLL mode. */
- edac_op_state = EDAC_OPSTATE_POLL;
-
- err = platform_driver_register(&tile_edac_mc_driver);
- if (err)
- return err;
-
- for (i = 0; i < TILE_MAX_MSHIMS; i++) {
- /*
- * Not all memory controllers are configured such as in the
- * case of a simulator. So we register only those mshims
- * that are configured by the hypervisor.
- */
- sprintf(hv_file, "mshim/%d", i);
- if (hv_dev_open((HV_VirtAddr)hv_file, 0) < 0)
- continue;
-
- pdev = platform_device_register_simple(DRV_NAME, i, NULL, 0);
- if (IS_ERR(pdev))
- continue;
- mshim_pdev[i] = pdev;
- num++;
- }
-
- if (num == 0) {
- platform_driver_unregister(&tile_edac_mc_driver);
- return -ENODEV;
- }
- return 0;
-}
-
-/*
- * Driver cleanup routine.
- */
-static void __exit tile_edac_exit(void)
-{
- int i;
-
- for (i = 0; i < TILE_MAX_MSHIMS; i++) {
- struct platform_device *pdev = mshim_pdev[i];
- if (!pdev)
- continue;
-
- platform_device_unregister(pdev);
- }
- platform_driver_unregister(&tile_edac_mc_driver);
-}
-
-module_init(tile_edac_init);
-module_exit(tile_edac_exit);