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authorChris Packham <chris.packham@alliedtelesis.co.nz>2019-07-12 05:46:58 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2019-08-29 07:58:01 +0100
commit23d103ae3e061b466dc68dd10a035dcd3b2de99a (patch)
tree8ddc4a8eb01e88473cc27355b6122754a8d2a49e /drivers/edac
parent7f6998a41257a8930ee5b6866ba56a25230841ed (diff)
ARM: 8891/1: EDAC: armada_xp: Add support for more SoCs
The Armada 38x and other integrated SoCs use a reduced pin count so the width of the SDRAM interface is smaller than the Armada XP SoCs. This means that the definition of "full" and "half" width is reduced from 64/32 to 32/16. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/armada_xp_edac.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c
index 3759a4fbbdee..7f227bdcbc84 100644
--- a/drivers/edac/armada_xp_edac.c
+++ b/drivers/edac/armada_xp_edac.c
@@ -332,6 +332,11 @@ static int axp_mc_probe(struct platform_device *pdev)
axp_mc_read_config(mci);
+ /* These SoCs have a reduced width bus */
+ if (of_machine_is_compatible("marvell,armada380") ||
+ of_machine_is_compatible("marvell,armadaxp-98dx3236"))
+ drvdata->width /= 2;
+
/* configure SBE threshold */
/* it seems that SBEs are not captured otherwise */
writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);