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| author | Dinh Nguyen <dinguyen@kernel.org> | 2021-11-08 14:08:54 -0600 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-11-12 18:17:59 +0000 |
| commit | 98d948eb833104a094517401ed8be26ba3ce9935 (patch) | |
| tree | 9f35171dd6d8615293e9675b35c6f4ac72344b27 /drivers/fpga/dfl-fme.h | |
| parent | 28b5eaf9712bbed90c2b5a5608d70a16b7950856 (diff) | |
spi: cadence-quadspi: fix write completion support
Some versions of the Cadence QSPI controller does not have the write
completion register implemented(CQSPI_REG_WR_COMPLETION_CTRL). On the
Intel SoCFPGA platform the CQSPI_REG_WR_COMPLETION_CTRL register is
not configured.
Add a quirk to not write to the CQSPI_REG_WR_COMPLETION_CTRL register.
Fixes: 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling)
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20211108200854.3616121-1-dinguyen@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/fpga/dfl-fme.h')
0 files changed, 0 insertions, 0 deletions