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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2018-05-15 23:05:58 +1000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2018-06-12 14:04:59 +1000
commitf3ca4834ac335bbf693d424326e4c93523a0c245 (patch)
tree87c2ddb063382784eb0425c2c404a51a36fe868c /drivers/fsi
parentb632642e4ce22f1fbf2094752e936565771b34f4 (diff)
fsi/fsi-master-gpio: Delay sampling of FSI data input
Most SoC GPIO implementations, including the Aspeed one, have synchronizers on the GPIO inputs. This means that the value read from a GPIO is a couple of clocks old, from whatever clock source feeds those synchronizers. In practice, this means that in no-delay mode, we are using a value that can potentially be a bit too old and too close to the clock edge establishing the data on the other side of the link. The voltage converters we use on some systems make this worse and sensitive to things like voltage fluctuations etc... This is, we believe, the cause of occasional CRC errors encountered during heavy activity on the LPC bus. This is fixed by introducing a dummy GPIO read before the actual data read. It slows down SBEFIFO by about 15% (less than any delay primitive) and the end result is so far solid. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Tested-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'drivers/fsi')
-rw-r--r--drivers/fsi/fsi-master-gpio.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/fsi/fsi-master-gpio.c b/drivers/fsi/fsi-master-gpio.c
index bd2b2cbd5eb5..e1bde9e3f855 100644
--- a/drivers/fsi/fsi-master-gpio.c
+++ b/drivers/fsi/fsi-master-gpio.c
@@ -97,6 +97,11 @@ static int sda_clock_in(struct fsi_master_gpio *master)
if (!master->no_delays)
ndelay(FSI_GPIO_STD_DLY);
gpiod_set_value(master->gpio_clk, 0);
+
+ /* Dummy read to feed the synchronizers */
+ gpiod_get_value(master->gpio_data);
+
+ /* Actual data read */
in = gpiod_get_value(master->gpio_data);
if (!master->no_delays)
ndelay(FSI_GPIO_STD_DLY);