Merge tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes, nothing too exciting about
  this.

  Some changes hit arch/sh and arch/arm but are well isolated and
  acknowledged by the respective arch maintainers.

  Core changes:

   - Dropped the chained IRQ setup callback into GPIOLIB as we got rid
     of the last users of that in this changeset.

  New drivers:

   - New driver for Ingenic X1830.

   - New driver for Freescale i.MX8MP.

  Driver enhancements:

   - Fix all remaining Intel drivers to pass their IRQ chips along with
     the GPIO chips.

   - Intel Baytrail allocates its irqchip dynamically.

   - Intel Lynxpoint is thoroughly rewritten and modernized.

   - Aspeed AST2600 pin muxing and configuration is much improved.

   - Qualcomm SC7180 functions are updated and wakeup interrupt map is
     provided.

   - A whole slew of Renesas SH-PFC cleanups and improvements.

   - Fix up the Intel DT bindings to use the generic YAML DT bindings
     schema (a first user of this)"

* tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: madera: Remove extra blank line
  pinctrl: qcom: Don't lock around irq_set_irq_wake()
  pinctrl: mvebu: armada-37xx: use use platform api
  gpio: Drop the chained IRQ handler assign function
  pinctrl: freescale: Add i.MX8MP pinctrl driver support
  dt-bindings: imx: Add pinctrl binding doc for i.MX8MP
  pinctrl: tigerlake: Tiger Lake uses _HID enumeration
  pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID
  pinctrl: iproc: Use platform_get_irq_optional() to avoid error message
  pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema
  pinctrl: intel: Pass irqchip when adding gpiochip
  pinctrl: intel: Add GPIO <-> pin mapping ranges via callback
  pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output
  pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins
  pinctrl: sunrisepoint: Add missing Interrupt Status register offset
  pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers
  pinctrl: artpec6: fix __iomem on reg in set
  pinctrl: ingenic: Use devm_platform_ioremap_resource()
  pinctrl: ingenic: Factorize irq_set_type function
  pinctrl: ingenic: Remove duplicated ingenic_chip_info structures
  ...

1 files changed, 1 insertions, 24 deletions

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 9d9ba56cb73d..99ac27a72e28 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1800,7 +1800,7 @@ EXPORT_SYMBOL_GPL(gpiochip_irqchip_irq_valid);
  * gpiochip_set_cascaded_irqchip() - connects a cascaded irqchip to a gpiochip
  * @gc: the gpiochip to set the irqchip chain to
  * @parent_irq: the irq number corresponding to the parent IRQ for this
- * chained irqchip
+ * cascaded irqchip
  * @parent_handler: the parent interrupt handler for the accumulated IRQ
  * coming out of the gpiochip. If the interrupt is nested rather than
  * cascaded, pass NULL in this handler argument
@@ -1843,29 +1843,6 @@ static void gpiochip_set_cascaded_irqchip(struct gpio_chip *gc,
 }
 
 /**
- * gpiochip_set_chained_irqchip() - connects a chained irqchip to a gpiochip
- * @gpiochip: the gpiochip to set the irqchip chain to
- * @irqchip: the irqchip to chain to the gpiochip
- * @parent_irq: the irq number corresponding to the parent IRQ for this
- * chained irqchip
- * @parent_handler: the parent interrupt handler for the accumulated IRQ
- * coming out of the gpiochip.
- */
-void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
-				  struct irq_chip *irqchip,
-				  unsigned int parent_irq,
-				  irq_flow_handler_t parent_handler)
-{
-	if (gpiochip->irq.threaded) {
-		chip_err(gpiochip, "tried to chain a threaded gpiochip\n");
-		return;
-	}
-
-	gpiochip_set_cascaded_irqchip(gpiochip, parent_irq, parent_handler);
-}
-EXPORT_SYMBOL_GPL(gpiochip_set_chained_irqchip);
-
-/**
  * gpiochip_set_nested_irqchip() - connects a nested irqchip to a gpiochip
  * @gpiochip: the gpiochip to set the irqchip nested handler to
  * @irqchip: the irqchip to nest to the gpiochip