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authorChristian König <christian.koenig@amd.com>2017-11-03 15:59:25 +0100
committerAlex Deucher <alexander.deucher@amd.com>2017-12-06 12:47:21 -0500
commitc47b41a79ab5e8faec9aea6c4a06c4d1e4d1132f (patch)
tree97820364b390c2b55ace5d1d27faf14c1f8193fb /drivers/gpu/drm/amd/amdgpu/cik.c
parent6f16b4fb60011cbc7d4530e112739ea4416c6ea6 (diff)
drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result
Not sure what that should originally been good for, but it doesn't seem to make any sense any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cik.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c40
1 files changed, 20 insertions, 20 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index a296f7bbe57c..8ba056a2a5da 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -757,72 +757,72 @@ static void cik_init_golden_registers(struct amdgpu_device *adev)
case CHIP_BONAIRE:
amdgpu_program_register_sequence(adev,
bonaire_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
+ ARRAY_SIZE(bonaire_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
bonaire_golden_registers,
- (const u32)ARRAY_SIZE(bonaire_golden_registers));
+ ARRAY_SIZE(bonaire_golden_registers));
amdgpu_program_register_sequence(adev,
bonaire_golden_common_registers,
- (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
+ ARRAY_SIZE(bonaire_golden_common_registers));
amdgpu_program_register_sequence(adev,
bonaire_golden_spm_registers,
- (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
+ ARRAY_SIZE(bonaire_golden_spm_registers));
break;
case CHIP_KABINI:
amdgpu_program_register_sequence(adev,
kalindi_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+ ARRAY_SIZE(kalindi_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
kalindi_golden_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_registers));
+ ARRAY_SIZE(kalindi_golden_registers));
amdgpu_program_register_sequence(adev,
kalindi_golden_common_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
+ ARRAY_SIZE(kalindi_golden_common_registers));
amdgpu_program_register_sequence(adev,
kalindi_golden_spm_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+ ARRAY_SIZE(kalindi_golden_spm_registers));
break;
case CHIP_MULLINS:
amdgpu_program_register_sequence(adev,
kalindi_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+ ARRAY_SIZE(kalindi_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
godavari_golden_registers,
- (const u32)ARRAY_SIZE(godavari_golden_registers));
+ ARRAY_SIZE(godavari_golden_registers));
amdgpu_program_register_sequence(adev,
kalindi_golden_common_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
+ ARRAY_SIZE(kalindi_golden_common_registers));
amdgpu_program_register_sequence(adev,
kalindi_golden_spm_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+ ARRAY_SIZE(kalindi_golden_spm_registers));
break;
case CHIP_KAVERI:
amdgpu_program_register_sequence(adev,
spectre_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
+ ARRAY_SIZE(spectre_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
spectre_golden_registers,
- (const u32)ARRAY_SIZE(spectre_golden_registers));
+ ARRAY_SIZE(spectre_golden_registers));
amdgpu_program_register_sequence(adev,
spectre_golden_common_registers,
- (const u32)ARRAY_SIZE(spectre_golden_common_registers));
+ ARRAY_SIZE(spectre_golden_common_registers));
amdgpu_program_register_sequence(adev,
spectre_golden_spm_registers,
- (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
+ ARRAY_SIZE(spectre_golden_spm_registers));
break;
case CHIP_HAWAII:
amdgpu_program_register_sequence(adev,
hawaii_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
+ ARRAY_SIZE(hawaii_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
hawaii_golden_registers,
- (const u32)ARRAY_SIZE(hawaii_golden_registers));
+ ARRAY_SIZE(hawaii_golden_registers));
amdgpu_program_register_sequence(adev,
hawaii_golden_common_registers,
- (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
+ ARRAY_SIZE(hawaii_golden_common_registers));
amdgpu_program_register_sequence(adev,
hawaii_golden_spm_registers,
- (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
+ ARRAY_SIZE(hawaii_golden_spm_registers));
break;
default:
break;