diff options
| author | Tao Zhou <tao.zhou1@amd.com> | 2019-07-29 17:19:57 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-02 10:30:38 -0500 |
| commit | b1a5895352dc1a154f1605702745ef2f63a5d797 (patch) | |
| tree | f9cabb3c4c59c1964f887dbeb9b73d2ec0611252 /drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | |
| parent | b7f92097f5bc5129cb386340ec54e6f40639d6e3 (diff) | |
drm/amdgpu: update the calc algorithm of umc ecc error count
the initial value of ecc error count can be adjusted
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/umc_v6_1.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c index 0ab2e96b4f77..64df37b860dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c @@ -98,9 +98,10 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); *error_count += - REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt); + (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - + UMC_V6_1_CE_CNT_INIT); /* clear the lower chip err count */ - WREG32(ecc_err_cnt_addr + umc_reg_offset, 0); + WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); /* select the higher chip and check the err counter */ ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, @@ -108,9 +109,10 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); *error_count += - REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt); + (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - + UMC_V6_1_CE_CNT_INIT); /* clear the higher chip err count */ - WREG32(ecc_err_cnt_addr + umc_reg_offset, 0); + WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); /* check for SRAM correctable error MCUMC_STATUS is a 64 bit register */ |