diff options
| author | Alan Harrison <Alan.Harrison@amd.com> | 2017-02-09 16:01:57 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-02-13 12:41:07 -0500 |
| commit | d50e5c24480f8a6e2918ecd998e65f990f88b0ee (patch) | |
| tree | 0f7885ab7d37e1e9ce8a4e7ea11c8c4fe8e6a1b9 /drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | |
| parent | c10c8f7c27103bd7ac02d041d9d6e97296d48fc1 (diff) | |
drm/amdgpu: Add to initialization of mmVCE_VCPU_CNTL register
Add a bit needed during initialization into the driver, where it is supposed
to be. Currently, this is happening in the VCE firmware, and although
functional, this is the correct place to perform this initialization.
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alan Harrison <Alan.Harrison@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vce_v3_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index a8c40eebdd78..a78298529f07 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -510,6 +510,8 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) WREG32(mmVCE_LMI_SWAP_CNTL, 0); WREG32(mmVCE_LMI_SWAP_CNTL1, 0); WREG32(mmVCE_LMI_VM_CTRL, 0); + WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000); + if (adev->asic_type >= CHIP_STONEY) { WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); |