diff options
author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2017-10-05 19:15:25 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-10-21 16:50:04 -0400 |
commit | 199e458aafc241a2792b3f8a99d5a11aa7726a7d (patch) | |
tree | 57535c6e7e7b23a7a76596ace76ea2b84dc0b73f /drivers/gpu/drm/amd/display/dc/core/dc_resource.c | |
parent | 215a6f05bcc18ffcd953a8527639ea1f571f4d81 (diff) |
drm/amd/display: Set addressable region as active + border
This ensures that we do not draw the blank region onscreen, and that we
do underscan instead.
Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_resource.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 303d7ec684d9..454a521a268d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -850,6 +850,20 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) */ pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; + /** + * KMD sends us h and v_addressable without the borders, which causes us sometimes to draw + * the blank region on-screen. Correct for this by adding the borders back to their + * respective addressable values, and by shifting recout. + */ + timing->h_addressable += timing->h_border_left + timing->h_border_right; + timing->v_addressable += timing->v_border_top + timing->v_border_bottom; + pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top; + pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left; + timing->v_border_top = 0; + timing->v_border_bottom = 0; + timing->h_border_left = 0; + timing->h_border_right = 0; + pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable; pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable; |