diff options
| author | Hugo Hu <hugo.hu@amd.com> | 2020-10-06 17:21:00 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-11-02 15:31:10 -0500 |
| commit | 3a372bed1e337efa450d8288bc75cfc9237b7bad (patch) | |
| tree | 7ba10106226aa2010cca196621c2a2f4d062bdad /drivers/gpu/drm/amd/display/dc/dce110 | |
| parent | cae78e0331459643e21b982e4833a6525a43e498 (diff) | |
drm/amd/display: correct eDP T9 delay
[Why]
The current end of T9 delay is relay on polling
sink status by DPCD. But the polling for sink
status change after NoVideoStream_flag set to 0.
[How]
Add function edp_add_delay_for_T9 to add T9 delay.
Move the sink status polling after blank.
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce110')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 3ac6c7b65a45..9f56887029ca 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -992,8 +992,6 @@ void dce110_edp_backlight_control( link_transmitter_control(ctx->dc_bios, &cntl); - - if (enable && link->dpcd_sink_ext_caps.bits.oled) msleep(OLED_POST_T7_DELAY); @@ -1004,7 +1002,7 @@ void dce110_edp_backlight_control( /*edp 1.2*/ if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) - edp_receiver_ready_T9(link); + edp_add_delay_for_T9(link); if (!enable && link->dpcd_sink_ext_caps.bits.oled) msleep(OLED_PRE_T11_DELAY); @@ -1145,12 +1143,14 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx) if (dc_is_dp_signal(pipe_ctx->stream->signal)) { pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); - /* - * After output is idle pattern some sinks need time to recognize the stream - * has changed or they enter protection state and hang. - */ - if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) + if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { + /* + * After output is idle pattern some sinks need time to recognize the stream + * has changed or they enter protection state and hang. + */ msleep(60); + } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) + edp_receiver_ready_T9(link); } } |