drm/amd/display: OPP refactor and consolidation for DCE.

Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5 files changed, 28 insertions, 380 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/Makefile b/drivers/gpu/drm/amd/display/dc/dce112/Makefile
index 34fba0730bed..2d536fbc60c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce112/Makefile
@@ -3,8 +3,7 @@
 # It provides the control and status of HW CRTC block.
 
 DCE112 = dce112_compressor.o dce112_hw_sequencer.o \
-dce112_resource.o dce112_mem_input.o dce112_opp_formatter.o \
-dce112_opp.o
+dce112_resource.o dce112_mem_input.o
 
 AMD_DAL_DCE112 = $(addprefix $(AMDDALPATH)/dc/dce112/,$(DCE112))
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.c
deleted file mode 100644
index 23c2d1086b3b..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/* include DCE11 register header files */
-#include "dce/dce_11_2_d.h"
-#include "dce/dce_11_2_sh_mask.h"
-
-#include "dce112_opp.h"
-
-#include "gamma_types.h"
-
-enum {
-	MAX_LUT_ENTRY = 256,
-	MAX_NUMBER_OF_ENTRIES = 256
-};
-
-/*****************************************/
-/* Constructor, Destructor               */
-/*****************************************/
-
-static struct opp_funcs funcs = {
-		.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
-		.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
-		.opp_set_csc_default = dce110_opp_set_csc_default,
-		.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
-		.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
-		.opp_set_regamma_mode = dce110_opp_set_regamma_mode,
-		.opp_destroy = dce110_opp_destroy,
-		.opp_program_fmt = dce112_opp_program_fmt,
-		.opp_program_bit_depth_reduction =
-				dce110_opp_program_bit_depth_reduction
-};
-
-bool dce112_opp_construct(struct dce110_opp *opp110,
-	struct dc_context *ctx,
-	uint32_t inst,
-	const struct dce110_opp_reg_offsets *offsets)
-{
-	opp110->base.funcs = &funcs;
-
-	opp110->base.ctx = ctx;
-
-	opp110->base.inst = inst;
-
-	opp110->offsets = *offsets;
-
-	return true;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.h
deleted file mode 100644
index 9443b87776c6..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_OPP_DCE112_H__
-#define __DC_OPP_DCE112_H__
-
-#include "dc_types.h"
-#include "opp.h"
-#include "../dce110/dce110_opp.h"
-#include "core_types.h"
-
-void dce112_opp_program_clamping_and_pixel_encoding(
-	struct output_pixel_processor *opp,
-	const struct clamping_and_pixel_encoding_params *params);
-
-void dce112_opp_program_fmt(
-		struct output_pixel_processor *opp,
-		struct bit_depth_reduction_params *fmt_bit_depth,
-		struct clamping_and_pixel_encoding_params *clamping);
-
-bool dce112_opp_construct(struct dce110_opp *opp110,
-	struct dc_context *ctx,
-	uint32_t inst,
-	const struct dce110_opp_reg_offsets *offsets);
-
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp_formatter.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp_formatter.c
deleted file mode 100644
index 2d9072138834..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_opp_formatter.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- *  and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "dce/dce_11_2_d.h"
-#include "dce/dce_11_2_sh_mask.h"
-
-#include "dce112_opp.h"
-
-#define FMT_REG(reg)\
-	(reg + opp110->offsets.fmt_offset)
-#define FMT_MEM_REG(reg)\
-	(reg + opp110->offsets.fmt_mem_offset)
-
-/**
- *	Set Clamping
- *	1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
- *		1 for 8 bpc
- *		2 for 10 bpc
- *		3 for 12 bpc
- *		7 for programable
- *	2) Enable clamp if Limited range requested
- */
-
-/**
- *	set_pixel_encoding
- *
- *	Set Pixel Encoding
- *		0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
- *		1: YCbCr 4:2:2
- *		2: YCbCr 4:2:0
- */
-static void set_pixel_encoding(
-	struct dce110_opp *opp110,
-	const struct clamping_and_pixel_encoding_params *params)
-{
-	uint32_t fmt_cntl_value;
-	uint32_t addr = FMT_REG(mmFMT_CONTROL);
-
-	/*RGB 4:4:4 or YCbCr 4:4:4 - 0; YCbCr 4:2:2 -1.*/
-	fmt_cntl_value = dm_read_reg(opp110->base.ctx, addr);
-
-	set_reg_field_value(fmt_cntl_value,
-		0,
-		FMT_CONTROL,
-		FMT_PIXEL_ENCODING);
-
-	/*00 - Pixels drop mode HW default*/
-	set_reg_field_value(fmt_cntl_value,
-		0,
-		FMT_CONTROL,
-		FMT_SUBSAMPLING_MODE);
-
-	/* By default no bypass*/
-	set_reg_field_value(fmt_cntl_value,
-		0,
-		FMT_CONTROL,
-		FMT_CBCR_BIT_REDUCTION_BYPASS);
-
-	if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-		set_reg_field_value(fmt_cntl_value,
-			1,
-			FMT_CONTROL,
-			FMT_PIXEL_ENCODING);
-
-		/*00 - Cb before Cr ,01 - Cr before Cb*/
-		set_reg_field_value(fmt_cntl_value,
-			0,
-			FMT_CONTROL,
-			FMT_SUBSAMPLING_ORDER);
-	}
-
-	if (params->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
-		set_reg_field_value(fmt_cntl_value,
-			2,
-			FMT_CONTROL,
-			FMT_PIXEL_ENCODING);
-
-		/* 02 - Subsampling mode, 3 taps*/
-		set_reg_field_value(fmt_cntl_value,
-			2,
-			FMT_CONTROL,
-			FMT_SUBSAMPLING_MODE);
-
-		/* 00 - Enable CbCr bit reduction bypass to preserve precision*/
-		set_reg_field_value(fmt_cntl_value,
-			1,
-			FMT_CONTROL,
-			FMT_CBCR_BIT_REDUCTION_BYPASS);
-	}
-	dm_write_reg(opp110->base.ctx, addr, fmt_cntl_value);
-
-}
-
-void dce112_opp_program_clamping_and_pixel_encoding(
-	struct output_pixel_processor *opp,
-	const struct clamping_and_pixel_encoding_params *params)
-{
-	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-
-	dce110_opp_set_clamping(opp110, params);
-	set_pixel_encoding(opp110, params);
-}
-
-static void program_formatter_420_memory(struct output_pixel_processor *opp)
-{
-	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-	uint32_t fmt_cntl_value;
-	uint32_t fmt_mem_cntl_value;
-	uint32_t fmt_cntl_addr = FMT_REG(mmFMT_CONTROL);
-	uint32_t fmt_mem_cntl_addr = FMT_MEM_REG(mmFMT_MEMORY0_CONTROL);
-
-	fmt_mem_cntl_value = dm_read_reg(opp110->base.ctx, fmt_mem_cntl_addr);
-	fmt_cntl_value = dm_read_reg(opp110->base.ctx, fmt_cntl_addr);
-	/* Program source select*/
-	/* Use HW default source select for FMT_MEMORYx_CONTROL */
-	/* Use that value for FMT_SRC_SELECT as well*/
-	set_reg_field_value(fmt_cntl_value,
-		get_reg_field_value(fmt_mem_cntl_value, FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL),
-		FMT_CONTROL,
-		FMT_SRC_SELECT);
-	dm_write_reg(opp110->base.ctx, fmt_cntl_addr, fmt_cntl_value);
-
-	/* Turn on the memory */
-	set_reg_field_value(fmt_mem_cntl_value,
-		0,
-		FMT_MEMORY0_CONTROL,
-		FMT420_MEM0_PWR_FORCE);
-	dm_write_reg(opp110->base.ctx, fmt_mem_cntl_addr, fmt_mem_cntl_value);
-}
-
-static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processor *opp)
-{
-	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-	uint32_t value;
-	uint32_t addr = FMT_REG(mmFMT_CONTROL);
-	uint8_t counter = 10;
-
-
-	value = dm_read_reg(opp110->base.ctx, addr);
-
-	/* clear previous phase lock status*/
-	set_reg_field_value(value,
-		1,
-		FMT_CONTROL,
-		FMT_420_PIXEL_PHASE_LOCKED_CLEAR);
-	dm_write_reg(opp110->base.ctx, addr, value);
-
-	/* poll until FMT_420_PIXEL_PHASE_LOCKED become 1*/
-	while (counter > 0) {
-		value = dm_read_reg(opp110->base.ctx, addr);
-
-		if (get_reg_field_value(
-			value,
-			FMT_CONTROL,
-			FMT_420_PIXEL_PHASE_LOCKED) == 1)
-			break;
-
-		msleep(10);
-		counter--;
-	}
-
-	if (counter == 0)
-		dm_logger_write(opp->ctx->logger, LOG_ERROR,
-				"%s:opp program formattter reset dig resync info time out.\n",
-				__func__);
-}
-
-void dce112_opp_program_fmt(
-		struct output_pixel_processor *opp,
-		struct bit_depth_reduction_params *fmt_bit_depth,
-		struct clamping_and_pixel_encoding_params *clamping)
-{
-	/* dithering is affected by <CrtcSourceSelect>, hence should be
-	 * programmed afterwards */
-
-	if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-		program_formatter_420_memory(opp);
-
-	dce110_opp_program_bit_depth_reduction(
-		opp,
-		fmt_bit_depth);
-
-	dce112_opp_program_clamping_and_pixel_encoding(
-		opp,
-		clamping);
-
-	if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-		program_formatter_reset_dig_resync_fifo(opp);
-
-	return;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 85d8b31acd02..2711893b71e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -39,7 +39,7 @@
 #include "dce/dce_link_encoder.h"
 #include "dce/dce_stream_encoder.h"
 #include "dce/dce_audio.h"
-#include "dce112/dce112_opp.h"
+#include "dce/dce_opp.h"
 #include "dce110/dce110_ipp.h"
 #include "dce/dce_clocks.h"
 #include "dce/dce_clock_source.h"
@@ -306,6 +306,28 @@ static const struct dce_stream_encoder_mask se_mask = {
 		SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
 };
 
+#define opp_regs(id)\
+[id] = {\
+	OPP_DCE_112_REG_LIST(id),\
+}
+
+static const struct dce_opp_registers opp_regs[] = {
+	opp_regs(0),
+	opp_regs(1),
+	opp_regs(2),
+	opp_regs(3),
+	opp_regs(4),
+	opp_regs(5)
+};
+
+static const struct dce_opp_shift opp_shift = {
+	OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
+};
+
+static const struct dce_opp_mask opp_mask = {
+	OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
+};
+
 #define audio_regs(id)\
 [id] = {\
 	AUD_COMMON_REG_LIST(id)\
@@ -328,42 +350,6 @@ static const struct dce_aduio_mask audio_mask = {
 		AUD_COMMON_MASK_SH_LIST(_MASK)
 };
 
-
-static const struct dce110_opp_reg_offsets dce112_opp_reg_offsets[] = {
-{
-	.fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-	.fmt_mem_offset = (mmFMT_MEMORY0_CONTROL - mmFMT_MEMORY0_CONTROL),
-	.dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-},
-{	.fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-	.fmt_mem_offset = (mmFMT_MEMORY1_CONTROL - mmFMT_MEMORY0_CONTROL),
-	.dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-},
-{	.fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-	.fmt_mem_offset = (mmFMT_MEMORY2_CONTROL - mmFMT_MEMORY0_CONTROL),
-	.dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-},
-{
-	.fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-	.fmt_mem_offset = (mmFMT_MEMORY3_CONTROL - mmFMT_MEMORY0_CONTROL),
-	.dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-},
-{	.fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-	.fmt_mem_offset = (mmFMT_MEMORY4_CONTROL - mmFMT_MEMORY0_CONTROL),
-	.dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-},
-{	.fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL),
-	.fmt_mem_offset = (mmFMT_MEMORY5_CONTROL - mmFMT_MEMORY0_CONTROL),
-	.dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL),
-	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-}
-};
-
 #define clk_src_regs(index, id)\
 [index] = {\
 	CS_COMMON_REG_LIST_DCE_112(id),\
@@ -631,8 +617,7 @@ void dce112_ipp_destroy(struct input_pixel_processor **ipp)
 
 struct output_pixel_processor *dce112_opp_create(
 	struct dc_context *ctx,
-	uint32_t inst,
-	const struct dce110_opp_reg_offsets *offset)
+	uint32_t inst)
 {
 	struct dce110_opp *opp =
 		dm_alloc(sizeof(struct dce110_opp));
@@ -640,8 +625,8 @@ struct output_pixel_processor *dce112_opp_create(
 	if (!opp)
 		return NULL;
 
-	if (dce112_opp_construct(opp,
-			ctx, inst, offset))
+	if (dce110_opp_construct(opp,
+			ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask))
 		return &opp->base;
 
 	BREAK_TO_DEBUGGER();
@@ -1381,8 +1366,7 @@ static bool construct(
 
 		pool->base.opps[i] = dce112_opp_create(
 			ctx,
-			i,
-			&dce112_opp_reg_offsets[i]);
+			i);
 		if (pool->base.opps[i] == NULL) {
 			BREAK_TO_DEBUGGER();
 			dm_error(