diff options
| author | Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> | 2023-06-01 16:09:32 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-15 10:45:27 -0400 |
| commit | a2c7356f526dba1aa5f49ba17c822e46dcf7d6f6 (patch) | |
| tree | eac436496045595c633cc142d9b2cd5f6ea712b7 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | f4bc8a43069c6268a49f064fdbf85ead5cc2bf04 (diff) | |
drm/amd/display: fix pixel rate update sequence
The k1/k2 pixel rate dividers in dccg should only be updated on stream enable
and do not actually depend on whether odm combine is active.
This removes an on flip update of these and fixes the calculate function
to ignore odm status for dp steams.
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 5934b1d70e48..b0a13eb8318c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1741,17 +1741,6 @@ static void dcn20_program_pipe( if (hws->funcs.setup_vupdate_interrupt) hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); - - if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { - unsigned int k1_div, k2_div; - - hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); - - dc->res_pool->dccg->funcs->set_pixel_rate_div( - dc->res_pool->dccg, - pipe_ctx->stream_res.tg->inst, - k1_div, k2_div); - } } if (pipe_ctx->update_flags.bits.odm) |